| mxsmmc.c (abb85be793180bdc0d9e30afe6c762669a5e0014) | mxsmmc.c (fa7a51cb8272bd6076ea4701fd6bdc65a68703ba) |
|---|---|
| 1/* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. --- 322 unchanged lines hidden (view full) --- 331} 332 333static int mxsmmc_init(struct mmc *mmc) 334{ 335 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 336 struct mxs_ssp_regs *ssp_regs = priv->regs; 337 338 /* Reset SSP */ | 1/* 2 * Freescale i.MX28 SSP MMC driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * Based on code from LTIB: 8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. --- 322 unchanged lines hidden (view full) --- 331} 332 333static int mxsmmc_init(struct mmc *mmc) 334{ 335 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; 336 struct mxs_ssp_regs *ssp_regs = priv->regs; 337 338 /* Reset SSP */ |
| 339 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); | 339 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); |
| 340 341 /* 8 bits word length in MMC mode */ 342 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 343 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 344 SSP_CTRL1_DMA_ENABLE, 345 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 346 347 /* Set initial bit clock 400 KHz */ --- 89 unchanged lines hidden --- | 340 341 /* 8 bits word length in MMC mode */ 342 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, 343 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | 344 SSP_CTRL1_DMA_ENABLE, 345 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); 346 347 /* Set initial bit clock 400 KHz */ --- 89 unchanged lines hidden --- |