util.c (1ad6364eeb4f578e423081d1748e8a3fdf1ab01d) util.c (34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85)
1/*
1/*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#ifdef CONFIG_PPC

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18
19/* To avoid 64-bit full-divides, we factor this here */
20#define ULL_2E12 2000000000000ULL
21#define UL_5POW12 244140625UL
22#define UL_2POW13 (1UL << 13)
23
24#define ULL_8FS 0xFFFFFFFFULL
25
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#ifdef CONFIG_PPC

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18
19/* To avoid 64-bit full-divides, we factor this here */
20#define ULL_2E12 2000000000000ULL
21#define UL_5POW12 244140625UL
22#define UL_2POW13 (1UL << 13)
23
24#define ULL_8FS 0xFFFFFFFFULL
25
26u32 fsl_ddr_get_version(void)
27{
28 struct ccsr_ddr __iomem *ddr;
29 u32 ver_major_minor_errata;
30
31 ddr = (void *)_DDR_ADDR;
32 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
33 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
34
35 return ver_major_minor_errata;
36}
37
26/*
27 * Round up mclk_ps to nearest 1 ps in memory controller code
28 * if the error is 0.5ps or more.
29 *
30 * If an imprecise data rate is too high due to rounding error
31 * propagation, compute a suitably rounded mclk_ps to compute
32 * a working memory controller configuration.
33 */

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170 puts("1");
171 break;
172 case SDRAM_TYPE_DDR2:
173 puts("2");
174 break;
175 case SDRAM_TYPE_DDR3:
176 puts("3");
177 break;
38/*
39 * Round up mclk_ps to nearest 1 ps in memory controller code
40 * if the error is 0.5ps or more.
41 *
42 * If an imprecise data rate is too high due to rounding error
43 * propagation, compute a suitably rounded mclk_ps to compute
44 * a working memory controller configuration.
45 */

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182 puts("1");
183 break;
184 case SDRAM_TYPE_DDR2:
185 puts("2");
186 break;
187 case SDRAM_TYPE_DDR3:
188 puts("3");
189 break;
190 case SDRAM_TYPE_DDR4:
191 puts("4");
192 break;
178 default:
179 puts("?");
180 break;
181 }
182
183 if (sdram_cfg & SDRAM_CFG_32_BE)
184 puts(", 32-bit");
185 else if (sdram_cfg & SDRAM_CFG_16_BE)
186 puts(", 16-bit");
187 else
188 puts(", 64-bit");
189
190 /* Calculate CAS latency based on timing cfg values */
193 default:
194 puts("?");
195 break;
196 }
197
198 if (sdram_cfg & SDRAM_CFG_32_BE)
199 puts(", 32-bit");
200 else if (sdram_cfg & SDRAM_CFG_16_BE)
201 puts(", 16-bit");
202 else
203 puts(", 64-bit");
204
205 /* Calculate CAS latency based on timing cfg values */
191 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
192 if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
193 cas_lat += (8 << 1);
206 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
207 if (fsl_ddr_get_version() <= 0x40400)
208 cas_lat += 1;
209 else
210 cas_lat += 2;
211 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
194 printf(", CL=%d", cas_lat >> 1);
195 if (cas_lat & 0x1)
196 puts(".5");
197
198 if (sdram_cfg & SDRAM_CFG_ECC_EN)
199 puts(", ECC on)");
200 else
201 puts(", ECC off)");

--- 73 unchanged lines hidden --- 		212 printf(", CL=%d", cas_lat >> 1);
213 if (cas_lat & 0x1)
214 puts(".5");
215
216 if (sdram_cfg & SDRAM_CFG_ECC_EN)
217 puts(", ECC on)");
218 else
219 puts(", ECC off)");

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