interactive.c (f15ea6e1d67782a1626d4a4922b6c20e380085e5) interactive.c (34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85)
1/*
1/*
2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
2 * Copyright 2010-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]

--- 137 unchanged lines hidden (view full) ---

148 const char *optname_str,
149 const char *value_str)
150{
151 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
152
153 static const struct options_string options[] = {
154 COMMON_TIMING(tckmin_x_ps),
155 COMMON_TIMING(tckmax_ps),
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]

--- 137 unchanged lines hidden (view full) ---

148 const char *optname_str,
149 const char *value_str)
150{
151 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
152
153 static const struct options_string options[] = {
154 COMMON_TIMING(tckmin_x_ps),
155 COMMON_TIMING(tckmax_ps),
156 COMMON_TIMING(tckmax_max_ps),
156 COMMON_TIMING(taamin_ps),
157 COMMON_TIMING(trcd_ps),
158 COMMON_TIMING(trp_ps),
159 COMMON_TIMING(tras_ps),
157 COMMON_TIMING(trcd_ps),
158 COMMON_TIMING(trp_ps),
159 COMMON_TIMING(tras_ps),
160 COMMON_TIMING(twr_ps),
160
161#ifdef CONFIG_SYS_FSL_DDR4
162 COMMON_TIMING(trfc1_ps),
163 COMMON_TIMING(trfc2_ps),
164 COMMON_TIMING(trfc4_ps),
165 COMMON_TIMING(trrds_ps),
166 COMMON_TIMING(trrdl_ps),
167 COMMON_TIMING(tccdl_ps),
168#else
161 COMMON_TIMING(twtr_ps),
162 COMMON_TIMING(trfc_ps),
163 COMMON_TIMING(trrd_ps),
169 COMMON_TIMING(twtr_ps),
170 COMMON_TIMING(trfc_ps),
171 COMMON_TIMING(trrd_ps),
172 COMMON_TIMING(trtp_ps),
173#endif
174 COMMON_TIMING(twr_ps),
164 COMMON_TIMING(trc_ps),
165 COMMON_TIMING(refresh_rate_ps),
175 COMMON_TIMING(trc_ps),
176 COMMON_TIMING(refresh_rate_ps),
177 COMMON_TIMING(extended_op_srt),
178#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
166 COMMON_TIMING(tis_ps),
167 COMMON_TIMING(tih_ps),
168 COMMON_TIMING(tds_ps),
169 COMMON_TIMING(tdh_ps),
179 COMMON_TIMING(tis_ps),
180 COMMON_TIMING(tih_ps),
181 COMMON_TIMING(tds_ps),
182 COMMON_TIMING(tdh_ps),
170 COMMON_TIMING(trtp_ps),
171 COMMON_TIMING(tdqsq_max_ps),
172 COMMON_TIMING(tqhs_ps),
183 COMMON_TIMING(tdqsq_max_ps),
184 COMMON_TIMING(tqhs_ps),
185#endif
173 COMMON_TIMING(ndimms_present),
186 COMMON_TIMING(ndimms_present),
174 COMMON_TIMING(lowest_common_SPD_caslat),
187 COMMON_TIMING(lowest_common_spd_caslat),
175 COMMON_TIMING(highest_common_derated_caslat),
176 COMMON_TIMING(additive_latency),
177 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
178 COMMON_TIMING(all_dimms_registered),
179 COMMON_TIMING(all_dimms_unbuffered),
180 COMMON_TIMING(all_dimms_ecc_capable),
181 COMMON_TIMING(total_mem),
182 COMMON_TIMING(base_address),

--- 23 unchanged lines hidden (view full) ---

206 DIMM_PARM(primary_sdram_width),
207 DIMM_PARM(ec_sdram_width),
208 DIMM_PARM(registered_dimm),
209 DIMM_PARM(device_width),
210
211 DIMM_PARM(n_row_addr),
212 DIMM_PARM(n_col_addr),
213 DIMM_PARM(edc_config),
188 COMMON_TIMING(highest_common_derated_caslat),
189 COMMON_TIMING(additive_latency),
190 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
191 COMMON_TIMING(all_dimms_registered),
192 COMMON_TIMING(all_dimms_unbuffered),
193 COMMON_TIMING(all_dimms_ecc_capable),
194 COMMON_TIMING(total_mem),
195 COMMON_TIMING(base_address),

--- 23 unchanged lines hidden (view full) ---

219 DIMM_PARM(primary_sdram_width),
220 DIMM_PARM(ec_sdram_width),
221 DIMM_PARM(registered_dimm),
222 DIMM_PARM(device_width),
223
224 DIMM_PARM(n_row_addr),
225 DIMM_PARM(n_col_addr),
226 DIMM_PARM(edc_config),
227#ifdef CONFIG_SYS_FSL_DDR4
228 DIMM_PARM(bank_addr_bits),
229 DIMM_PARM(bank_group_bits),
230#else
214 DIMM_PARM(n_banks_per_sdram_device),
231 DIMM_PARM(n_banks_per_sdram_device),
232#endif
215 DIMM_PARM(burst_lengths_bitmask),
216 DIMM_PARM(row_density),
217
218 DIMM_PARM(tckmin_x_ps),
219 DIMM_PARM(tckmin_x_minus_1_ps),
220 DIMM_PARM(tckmin_x_minus_2_ps),
221 DIMM_PARM(tckmax_ps),
222
223 DIMM_PARM(caslat_x),
224 DIMM_PARM(caslat_x_minus_1),
225 DIMM_PARM(caslat_x_minus_2),
226
227 DIMM_PARM(caslat_lowest_derated),
228
229 DIMM_PARM(trcd_ps),
230 DIMM_PARM(trp_ps),
231 DIMM_PARM(tras_ps),
233 DIMM_PARM(burst_lengths_bitmask),
234 DIMM_PARM(row_density),
235
236 DIMM_PARM(tckmin_x_ps),
237 DIMM_PARM(tckmin_x_minus_1_ps),
238 DIMM_PARM(tckmin_x_minus_2_ps),
239 DIMM_PARM(tckmax_ps),
240
241 DIMM_PARM(caslat_x),
242 DIMM_PARM(caslat_x_minus_1),
243 DIMM_PARM(caslat_x_minus_2),
244
245 DIMM_PARM(caslat_lowest_derated),
246
247 DIMM_PARM(trcd_ps),
248 DIMM_PARM(trp_ps),
249 DIMM_PARM(tras_ps),
250#ifdef CONFIG_SYS_FSL_DDR4
251 DIMM_PARM(trfc1_ps),
252 DIMM_PARM(trfc2_ps),
253 DIMM_PARM(trfc4_ps),
254 DIMM_PARM(trrds_ps),
255 DIMM_PARM(trrdl_ps),
256 DIMM_PARM(tccdl_ps),
257#else
232 DIMM_PARM(twr_ps),
233 DIMM_PARM(twtr_ps),
234 DIMM_PARM(trfc_ps),
235 DIMM_PARM(trrd_ps),
258 DIMM_PARM(twr_ps),
259 DIMM_PARM(twtr_ps),
260 DIMM_PARM(trfc_ps),
261 DIMM_PARM(trrd_ps),
262 DIMM_PARM(trtp_ps),
263#endif
236 DIMM_PARM(trc_ps),
237 DIMM_PARM(refresh_rate_ps),
264 DIMM_PARM(trc_ps),
265 DIMM_PARM(refresh_rate_ps),
266 DIMM_PARM(extended_op_srt),
238
267
268#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
239 DIMM_PARM(tis_ps),
240 DIMM_PARM(tih_ps),
241 DIMM_PARM(tds_ps),
242 DIMM_PARM(tdh_ps),
269 DIMM_PARM(tis_ps),
270 DIMM_PARM(tih_ps),
271 DIMM_PARM(tds_ps),
272 DIMM_PARM(tdh_ps),
243 DIMM_PARM(trtp_ps),
244 DIMM_PARM(tdqsq_max_ps),
245 DIMM_PARM(tqhs_ps),
273 DIMM_PARM(tdqsq_max_ps),
274 DIMM_PARM(tqhs_ps),
275#endif
246
247 DIMM_PARM(rank_density),
248 DIMM_PARM(capacity),
249 DIMM_PARM(base_address),
250 };
251
252 static const unsigned int n_opts = ARRAY_SIZE(options);
253

--- 11 unchanged lines hidden (view full) ---

265 DIMM_PARM(primary_sdram_width),
266 DIMM_PARM(ec_sdram_width),
267 DIMM_PARM(registered_dimm),
268 DIMM_PARM(device_width),
269
270 DIMM_PARM(n_row_addr),
271 DIMM_PARM(n_col_addr),
272 DIMM_PARM(edc_config),
276
277 DIMM_PARM(rank_density),
278 DIMM_PARM(capacity),
279 DIMM_PARM(base_address),
280 };
281
282 static const unsigned int n_opts = ARRAY_SIZE(options);
283

--- 11 unchanged lines hidden (view full) ---

295 DIMM_PARM(primary_sdram_width),
296 DIMM_PARM(ec_sdram_width),
297 DIMM_PARM(registered_dimm),
298 DIMM_PARM(device_width),
299
300 DIMM_PARM(n_row_addr),
301 DIMM_PARM(n_col_addr),
302 DIMM_PARM(edc_config),
303#ifdef CONFIG_SYS_FSL_DDR4
304 DIMM_PARM(bank_addr_bits),
305 DIMM_PARM(bank_group_bits),
306#else
273 DIMM_PARM(n_banks_per_sdram_device),
307 DIMM_PARM(n_banks_per_sdram_device),
308#endif
274
275 DIMM_PARM(tckmin_x_ps),
276 DIMM_PARM(tckmin_x_minus_1_ps),
277 DIMM_PARM(tckmin_x_minus_2_ps),
278 DIMM_PARM(tckmax_ps),
279
280 DIMM_PARM(caslat_x),
281 DIMM_PARM(taa_ps),
282 DIMM_PARM(caslat_x_minus_1),
283 DIMM_PARM(caslat_x_minus_2),
284 DIMM_PARM(caslat_lowest_derated),
285
286 DIMM_PARM(trcd_ps),
287 DIMM_PARM(trp_ps),
288 DIMM_PARM(tras_ps),
309
310 DIMM_PARM(tckmin_x_ps),
311 DIMM_PARM(tckmin_x_minus_1_ps),
312 DIMM_PARM(tckmin_x_minus_2_ps),
313 DIMM_PARM(tckmax_ps),
314
315 DIMM_PARM(caslat_x),
316 DIMM_PARM(taa_ps),
317 DIMM_PARM(caslat_x_minus_1),
318 DIMM_PARM(caslat_x_minus_2),
319 DIMM_PARM(caslat_lowest_derated),
320
321 DIMM_PARM(trcd_ps),
322 DIMM_PARM(trp_ps),
323 DIMM_PARM(tras_ps),
324#ifdef CONFIG_SYS_FSL_DDR4
325 DIMM_PARM(trfc1_ps),
326 DIMM_PARM(trfc2_ps),
327 DIMM_PARM(trfc4_ps),
328 DIMM_PARM(trrds_ps),
329 DIMM_PARM(trrdl_ps),
330 DIMM_PARM(tccdl_ps),
331#else
289 DIMM_PARM(twr_ps),
290 DIMM_PARM(twtr_ps),
291 DIMM_PARM(trfc_ps),
292 DIMM_PARM(trrd_ps),
332 DIMM_PARM(twr_ps),
333 DIMM_PARM(twtr_ps),
334 DIMM_PARM(trfc_ps),
335 DIMM_PARM(trrd_ps),
336 DIMM_PARM(trtp_ps),
337#endif
293 DIMM_PARM(trc_ps),
294 DIMM_PARM(refresh_rate_ps),
295
338 DIMM_PARM(trc_ps),
339 DIMM_PARM(refresh_rate_ps),
340
341#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
296 DIMM_PARM(tis_ps),
297 DIMM_PARM(tih_ps),
298 DIMM_PARM(tds_ps),
299 DIMM_PARM(tdh_ps),
342 DIMM_PARM(tis_ps),
343 DIMM_PARM(tih_ps),
344 DIMM_PARM(tds_ps),
345 DIMM_PARM(tdh_ps),
300 DIMM_PARM(trtp_ps),
301 DIMM_PARM(tdqsq_max_ps),
302 DIMM_PARM(tqhs_ps),
346 DIMM_PARM(tdqsq_max_ps),
347 DIMM_PARM(tqhs_ps),
348#endif
303 };
304 static const unsigned int n_opts = ARRAY_SIZE(options);
305
306 if (pdimm->n_ranks == 0) {
307 printf("DIMM not present\n");
308 return;
309 }
310 printf("DIMM organization parameters:\n");

--- 10 unchanged lines hidden (view full) ---

321 pdimm->base_address & 0xFFFFFFFF);
322 print_option_table(options, n_opts, pdimm);
323}
324
325static void print_lowest_common_dimm_parameters(
326 const common_timing_params_t *plcd_dimm_params)
327{
328 static const struct options_string options[] = {
349 };
350 static const unsigned int n_opts = ARRAY_SIZE(options);
351
352 if (pdimm->n_ranks == 0) {
353 printf("DIMM not present\n");
354 return;
355 }
356 printf("DIMM organization parameters:\n");

--- 10 unchanged lines hidden (view full) ---

367 pdimm->base_address & 0xFFFFFFFF);
368 print_option_table(options, n_opts, pdimm);
369}
370
371static void print_lowest_common_dimm_parameters(
372 const common_timing_params_t *plcd_dimm_params)
373{
374 static const struct options_string options[] = {
329 COMMON_TIMING(tckmax_max_ps),
375 COMMON_TIMING(taamin_ps),
330 COMMON_TIMING(trcd_ps),
331 COMMON_TIMING(trp_ps),
332 COMMON_TIMING(tras_ps),
376 COMMON_TIMING(trcd_ps),
377 COMMON_TIMING(trp_ps),
378 COMMON_TIMING(tras_ps),
333 COMMON_TIMING(twr_ps),
379#ifdef CONFIG_SYS_FSL_DDR4
380 COMMON_TIMING(trfc1_ps),
381 COMMON_TIMING(trfc2_ps),
382 COMMON_TIMING(trfc4_ps),
383 COMMON_TIMING(trrds_ps),
384 COMMON_TIMING(trrdl_ps),
385 COMMON_TIMING(tccdl_ps),
386#else
334 COMMON_TIMING(twtr_ps),
335 COMMON_TIMING(trfc_ps),
336 COMMON_TIMING(trrd_ps),
387 COMMON_TIMING(twtr_ps),
388 COMMON_TIMING(trfc_ps),
389 COMMON_TIMING(trrd_ps),
390 COMMON_TIMING(trtp_ps),
391#endif
392 COMMON_TIMING(twr_ps),
337 COMMON_TIMING(trc_ps),
338 COMMON_TIMING(refresh_rate_ps),
393 COMMON_TIMING(trc_ps),
394 COMMON_TIMING(refresh_rate_ps),
395 COMMON_TIMING(extended_op_srt),
396#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
339 COMMON_TIMING(tis_ps),
397 COMMON_TIMING(tis_ps),
398 COMMON_TIMING(tih_ps),
340 COMMON_TIMING(tds_ps),
341 COMMON_TIMING(tdh_ps),
399 COMMON_TIMING(tds_ps),
400 COMMON_TIMING(tdh_ps),
342 COMMON_TIMING(trtp_ps),
343 COMMON_TIMING(tdqsq_max_ps),
344 COMMON_TIMING(tqhs_ps),
401 COMMON_TIMING(tdqsq_max_ps),
402 COMMON_TIMING(tqhs_ps),
345 COMMON_TIMING(lowest_common_SPD_caslat),
403#endif
404 COMMON_TIMING(lowest_common_spd_caslat),
346 COMMON_TIMING(highest_common_derated_caslat),
347 COMMON_TIMING(additive_latency),
348 COMMON_TIMING(ndimms_present),
349 COMMON_TIMING(all_dimms_registered),
350 COMMON_TIMING(all_dimms_unbuffered),
351 COMMON_TIMING(all_dimms_ecc_capable),
352 };
353 static const unsigned int n_opts = ARRAY_SIZE(options);

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455 CTRL_OPTIONS(rcw_1),
456 CTRL_OPTIONS(rcw_2),
457 CTRL_OPTIONS(ddr_cdr1),
458 CTRL_OPTIONS(ddr_cdr2),
459 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
460 CTRL_OPTIONS(tfaw_window_four_activates_ps),
461 CTRL_OPTIONS(trwt_override),
462 CTRL_OPTIONS(trwt),
405 COMMON_TIMING(highest_common_derated_caslat),
406 COMMON_TIMING(additive_latency),
407 COMMON_TIMING(ndimms_present),
408 COMMON_TIMING(all_dimms_registered),
409 COMMON_TIMING(all_dimms_unbuffered),
410 COMMON_TIMING(all_dimms_ecc_capable),
411 };
412 static const unsigned int n_opts = ARRAY_SIZE(options);

--- 101 unchanged lines hidden (view full) ---

514 CTRL_OPTIONS(rcw_1),
515 CTRL_OPTIONS(rcw_2),
516 CTRL_OPTIONS(ddr_cdr1),
517 CTRL_OPTIONS(ddr_cdr2),
518 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
519 CTRL_OPTIONS(tfaw_window_four_activates_ps),
520 CTRL_OPTIONS(trwt_override),
521 CTRL_OPTIONS(trwt),
522 CTRL_OPTIONS(rtt_override),
523 CTRL_OPTIONS(rtt_override_value),
524 CTRL_OPTIONS(rtt_wr_override_value),
463 };
464
465 static const unsigned int n_opts = ARRAY_SIZE(options);
466
467 if (handle_option_table(options, n_opts, p,
468 optname_str, value_str))
469 return;
470

--- 29 unchanged lines hidden (view full) ---

500 CFG_REGS_CS(3, config_2),
501#endif
502 CFG_REGS(timing_cfg_3),
503 CFG_REGS(timing_cfg_0),
504 CFG_REGS(timing_cfg_1),
505 CFG_REGS(timing_cfg_2),
506 CFG_REGS(ddr_sdram_cfg),
507 CFG_REGS(ddr_sdram_cfg_2),
525 };
526
527 static const unsigned int n_opts = ARRAY_SIZE(options);
528
529 if (handle_option_table(options, n_opts, p,
530 optname_str, value_str))
531 return;
532

--- 29 unchanged lines hidden (view full) ---

562 CFG_REGS_CS(3, config_2),
563#endif
564 CFG_REGS(timing_cfg_3),
565 CFG_REGS(timing_cfg_0),
566 CFG_REGS(timing_cfg_1),
567 CFG_REGS(timing_cfg_2),
568 CFG_REGS(ddr_sdram_cfg),
569 CFG_REGS(ddr_sdram_cfg_2),
570 CFG_REGS(ddr_sdram_cfg_3),
508 CFG_REGS(ddr_sdram_mode),
509 CFG_REGS(ddr_sdram_mode_2),
510 CFG_REGS(ddr_sdram_mode_3),
511 CFG_REGS(ddr_sdram_mode_4),
512 CFG_REGS(ddr_sdram_mode_5),
513 CFG_REGS(ddr_sdram_mode_6),
514 CFG_REGS(ddr_sdram_mode_7),
515 CFG_REGS(ddr_sdram_mode_8),
571 CFG_REGS(ddr_sdram_mode),
572 CFG_REGS(ddr_sdram_mode_2),
573 CFG_REGS(ddr_sdram_mode_3),
574 CFG_REGS(ddr_sdram_mode_4),
575 CFG_REGS(ddr_sdram_mode_5),
576 CFG_REGS(ddr_sdram_mode_6),
577 CFG_REGS(ddr_sdram_mode_7),
578 CFG_REGS(ddr_sdram_mode_8),
579#ifdef CONFIG_SYS_FSL_DDR4
580 CFG_REGS(ddr_sdram_mode_9),
581 CFG_REGS(ddr_sdram_mode_10),
582 CFG_REGS(ddr_sdram_mode_11),
583 CFG_REGS(ddr_sdram_mode_12),
584 CFG_REGS(ddr_sdram_mode_13),
585 CFG_REGS(ddr_sdram_mode_14),
586 CFG_REGS(ddr_sdram_mode_15),
587 CFG_REGS(ddr_sdram_mode_16),
588#endif
516 CFG_REGS(ddr_sdram_interval),
517 CFG_REGS(ddr_data_init),
518 CFG_REGS(ddr_sdram_clk_cntl),
519 CFG_REGS(ddr_init_addr),
520 CFG_REGS(ddr_init_ext_addr),
521 CFG_REGS(timing_cfg_4),
522 CFG_REGS(timing_cfg_5),
589 CFG_REGS(ddr_sdram_interval),
590 CFG_REGS(ddr_data_init),
591 CFG_REGS(ddr_sdram_clk_cntl),
592 CFG_REGS(ddr_init_addr),
593 CFG_REGS(ddr_init_ext_addr),
594 CFG_REGS(timing_cfg_4),
595 CFG_REGS(timing_cfg_5),
596#ifdef CONFIG_SYS_FSL_DDR4
597 CFG_REGS(timing_cfg_6),
598 CFG_REGS(timing_cfg_7),
599 CFG_REGS(timing_cfg_8),
600 CFG_REGS(timing_cfg_9),
601#endif
523 CFG_REGS(ddr_zq_cntl),
524 CFG_REGS(ddr_wrlvl_cntl),
525 CFG_REGS(ddr_wrlvl_cntl_2),
526 CFG_REGS(ddr_wrlvl_cntl_3),
527 CFG_REGS(ddr_sr_cntr),
528 CFG_REGS(ddr_sdram_rcw_1),
529 CFG_REGS(ddr_sdram_rcw_2),
530 CFG_REGS(ddr_cdr1),
531 CFG_REGS(ddr_cdr2),
602 CFG_REGS(ddr_zq_cntl),
603 CFG_REGS(ddr_wrlvl_cntl),
604 CFG_REGS(ddr_wrlvl_cntl_2),
605 CFG_REGS(ddr_wrlvl_cntl_3),
606 CFG_REGS(ddr_sr_cntr),
607 CFG_REGS(ddr_sdram_rcw_1),
608 CFG_REGS(ddr_sdram_rcw_2),
609 CFG_REGS(ddr_cdr1),
610 CFG_REGS(ddr_cdr2),
611 CFG_REGS(dq_map_0),
612 CFG_REGS(dq_map_1),
613 CFG_REGS(dq_map_2),
614 CFG_REGS(dq_map_3),
532 CFG_REGS(err_disable),
533 CFG_REGS(err_int_en),
534 CFG_REGS(ddr_eor),
535 };
536 static const unsigned int n_opts = ARRAY_SIZE(options);
537
538 print_option_table(options, n_opts, ddr);
539

--- 29 unchanged lines hidden (view full) ---

569 CFG_REGS_CS(3, config_2),
570#endif
571 CFG_REGS(timing_cfg_3),
572 CFG_REGS(timing_cfg_0),
573 CFG_REGS(timing_cfg_1),
574 CFG_REGS(timing_cfg_2),
575 CFG_REGS(ddr_sdram_cfg),
576 CFG_REGS(ddr_sdram_cfg_2),
615 CFG_REGS(err_disable),
616 CFG_REGS(err_int_en),
617 CFG_REGS(ddr_eor),
618 };
619 static const unsigned int n_opts = ARRAY_SIZE(options);
620
621 print_option_table(options, n_opts, ddr);
622

--- 29 unchanged lines hidden (view full) ---

652 CFG_REGS_CS(3, config_2),
653#endif
654 CFG_REGS(timing_cfg_3),
655 CFG_REGS(timing_cfg_0),
656 CFG_REGS(timing_cfg_1),
657 CFG_REGS(timing_cfg_2),
658 CFG_REGS(ddr_sdram_cfg),
659 CFG_REGS(ddr_sdram_cfg_2),
660 CFG_REGS(ddr_sdram_cfg_3),
577 CFG_REGS(ddr_sdram_mode),
578 CFG_REGS(ddr_sdram_mode_2),
579 CFG_REGS(ddr_sdram_mode_3),
580 CFG_REGS(ddr_sdram_mode_4),
581 CFG_REGS(ddr_sdram_mode_5),
582 CFG_REGS(ddr_sdram_mode_6),
583 CFG_REGS(ddr_sdram_mode_7),
584 CFG_REGS(ddr_sdram_mode_8),
661 CFG_REGS(ddr_sdram_mode),
662 CFG_REGS(ddr_sdram_mode_2),
663 CFG_REGS(ddr_sdram_mode_3),
664 CFG_REGS(ddr_sdram_mode_4),
665 CFG_REGS(ddr_sdram_mode_5),
666 CFG_REGS(ddr_sdram_mode_6),
667 CFG_REGS(ddr_sdram_mode_7),
668 CFG_REGS(ddr_sdram_mode_8),
669#ifdef CONFIG_SYS_FSL_DDR4
670 CFG_REGS(ddr_sdram_mode_9),
671 CFG_REGS(ddr_sdram_mode_10),
672 CFG_REGS(ddr_sdram_mode_11),
673 CFG_REGS(ddr_sdram_mode_12),
674 CFG_REGS(ddr_sdram_mode_13),
675 CFG_REGS(ddr_sdram_mode_14),
676 CFG_REGS(ddr_sdram_mode_15),
677 CFG_REGS(ddr_sdram_mode_16),
678#endif
585 CFG_REGS(ddr_sdram_interval),
586 CFG_REGS(ddr_data_init),
587 CFG_REGS(ddr_sdram_clk_cntl),
588 CFG_REGS(ddr_init_addr),
589 CFG_REGS(ddr_init_ext_addr),
590 CFG_REGS(timing_cfg_4),
591 CFG_REGS(timing_cfg_5),
679 CFG_REGS(ddr_sdram_interval),
680 CFG_REGS(ddr_data_init),
681 CFG_REGS(ddr_sdram_clk_cntl),
682 CFG_REGS(ddr_init_addr),
683 CFG_REGS(ddr_init_ext_addr),
684 CFG_REGS(timing_cfg_4),
685 CFG_REGS(timing_cfg_5),
686#ifdef CONFIG_SYS_FSL_DDR4
687 CFG_REGS(timing_cfg_6),
688 CFG_REGS(timing_cfg_7),
689 CFG_REGS(timing_cfg_8),
690 CFG_REGS(timing_cfg_9),
691#endif
592 CFG_REGS(ddr_zq_cntl),
593 CFG_REGS(ddr_wrlvl_cntl),
594 CFG_REGS(ddr_wrlvl_cntl_2),
595 CFG_REGS(ddr_wrlvl_cntl_3),
596 CFG_REGS(ddr_sr_cntr),
597 CFG_REGS(ddr_sdram_rcw_1),
598 CFG_REGS(ddr_sdram_rcw_2),
599 CFG_REGS(ddr_cdr1),
600 CFG_REGS(ddr_cdr2),
692 CFG_REGS(ddr_zq_cntl),
693 CFG_REGS(ddr_wrlvl_cntl),
694 CFG_REGS(ddr_wrlvl_cntl_2),
695 CFG_REGS(ddr_wrlvl_cntl_3),
696 CFG_REGS(ddr_sr_cntr),
697 CFG_REGS(ddr_sdram_rcw_1),
698 CFG_REGS(ddr_sdram_rcw_2),
699 CFG_REGS(ddr_cdr1),
700 CFG_REGS(ddr_cdr2),
701 CFG_REGS(dq_map_0),
702 CFG_REGS(dq_map_1),
703 CFG_REGS(dq_map_2),
704 CFG_REGS(dq_map_3),
601 CFG_REGS(err_disable),
602 CFG_REGS(err_int_en),
603 CFG_REGS(ddr_sdram_rcw_2),
604 CFG_REGS(ddr_sdram_rcw_2),
605 CFG_REGS(ddr_eor),
606 };
607 static const unsigned int n_opts = ARRAY_SIZE(options);
608

--- 91 unchanged lines hidden (view full) ---

700 CTRL_OPTIONS(rcw_1),
701 CTRL_OPTIONS(rcw_2),
702 CTRL_OPTIONS_HEX(ddr_cdr1),
703 CTRL_OPTIONS_HEX(ddr_cdr2),
704 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
705 CTRL_OPTIONS(tfaw_window_four_activates_ps),
706 CTRL_OPTIONS(trwt_override),
707 CTRL_OPTIONS(trwt),
705 CFG_REGS(err_disable),
706 CFG_REGS(err_int_en),
707 CFG_REGS(ddr_sdram_rcw_2),
708 CFG_REGS(ddr_sdram_rcw_2),
709 CFG_REGS(ddr_eor),
710 };
711 static const unsigned int n_opts = ARRAY_SIZE(options);
712

--- 91 unchanged lines hidden (view full) ---

804 CTRL_OPTIONS(rcw_1),
805 CTRL_OPTIONS(rcw_2),
806 CTRL_OPTIONS_HEX(ddr_cdr1),
807 CTRL_OPTIONS_HEX(ddr_cdr2),
808 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
809 CTRL_OPTIONS(tfaw_window_four_activates_ps),
810 CTRL_OPTIONS(trwt_override),
811 CTRL_OPTIONS(trwt),
812 CTRL_OPTIONS(rtt_override),
813 CTRL_OPTIONS(rtt_override_value),
814 CTRL_OPTIONS(rtt_wr_override_value),
708 };
709 static const unsigned int n_opts = ARRAY_SIZE(options);
710
711 print_option_table(options, n_opts, popts);
712}
713
714#ifdef CONFIG_SYS_FSL_DDR1
715void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)

--- 524 unchanged lines hidden (view full) ---

1240 printf("%-3d-%3d: ", 176, 255);
1241 for (i = 176; i <= 255; i++)
1242 printf("%02x", spd->cust[i - 176]);
1243 printf(" Mfg's Specific Data\n");
1244
1245}
1246#endif
1247
815 };
816 static const unsigned int n_opts = ARRAY_SIZE(options);
817
818 print_option_table(options, n_opts, popts);
819}
820
821#ifdef CONFIG_SYS_FSL_DDR1
822void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)

--- 524 unchanged lines hidden (view full) ---

1347 printf("%-3d-%3d: ", 176, 255);
1348 for (i = 176; i <= 255; i++)
1349 printf("%02x", spd->cust[i - 176]);
1350 printf(" Mfg's Specific Data\n");
1351
1352}
1353#endif
1354
1355#ifdef CONFIG_SYS_FSL_DDR4
1356void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1357{
1358 unsigned int i;
1359
1360 /* General Section: Bytes 0-127 */
1361
1362#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
1363#define PRINT_NNXXS(n0, n1, x0, x1, s) \
1364 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1365
1366 PRINT_NXS(0, spd->info_size_crc,
1367 "info_size_crc bytes written into serial memory, CRC coverage");
1368 PRINT_NXS(1, spd->spd_rev,
1369 "spd_rev SPD Revision");
1370 PRINT_NXS(2, spd->mem_type,
1371 "mem_type Key Byte / DRAM Device Type");
1372 PRINT_NXS(3, spd->module_type,
1373 "module_type Key Byte / Module Type");
1374 PRINT_NXS(4, spd->density_banks,
1375 "density_banks SDRAM Density and Banks");
1376 PRINT_NXS(5, spd->addressing,
1377 "addressing SDRAM Addressing");
1378 PRINT_NXS(6, spd->package_type,
1379 "package_type Package type");
1380 PRINT_NXS(7, spd->opt_feature,
1381 "opt_feature Optional features");
1382 PRINT_NXS(8, spd->thermal_ref,
1383 "thermal_ref Thermal and Refresh options");
1384 PRINT_NXS(9, spd->oth_opt_features,
1385 "oth_opt_features Other SDRAM optional features");
1386 PRINT_NXS(10, spd->res_10,
1387 "res_10 Reserved");
1388 PRINT_NXS(11, spd->module_vdd,
1389 "module_vdd Module Nominal Voltage, VDD");
1390 PRINT_NXS(12, spd->organization,
1391 "organization Module Organization");
1392 PRINT_NXS(13, spd->bus_width,
1393 "bus_width Module Memory Bus Width");
1394 PRINT_NXS(14, spd->therm_sensor,
1395 "therm_sensor Module Thermal Sensor");
1396 PRINT_NXS(15, spd->ext_type,
1397 "ext_type Extended module type");
1398 PRINT_NXS(16, spd->res_16,
1399 "res_16 Reserved");
1400 PRINT_NXS(17, spd->timebases,
1401 "timebases MTb and FTB");
1402 PRINT_NXS(18, spd->tck_min,
1403 "tck_min tCKAVGmin");
1404 PRINT_NXS(19, spd->tck_max,
1405 "tck_max TCKAVGmax");
1406 PRINT_NXS(20, spd->caslat_b1,
1407 "caslat_b1 CAS latencies, 1st byte");
1408 PRINT_NXS(21, spd->caslat_b2,
1409 "caslat_b2 CAS latencies, 2nd byte");
1410 PRINT_NXS(22, spd->caslat_b3,
1411 "caslat_b3 CAS latencies, 3rd byte ");
1412 PRINT_NXS(23, spd->caslat_b4,
1413 "caslat_b4 CAS latencies, 4th byte");
1414 PRINT_NXS(24, spd->taa_min,
1415 "taa_min Min CAS Latency Time");
1416 PRINT_NXS(25, spd->trcd_min,
1417 "trcd_min Min RAS# to CAS# Delay Time");
1418 PRINT_NXS(26, spd->trp_min,
1419 "trp_min Min Row Precharge Delay Time");
1420 PRINT_NXS(27, spd->tras_trc_ext,
1421 "tras_trc_ext Upper Nibbles for tRAS and tRC");
1422 PRINT_NXS(28, spd->tras_min_lsb,
1423 "tras_min_lsb tRASmin, lsb");
1424 PRINT_NXS(29, spd->trc_min_lsb,
1425 "trc_min_lsb tRCmin, lsb");
1426 PRINT_NXS(30, spd->trfc1_min_lsb,
1427 "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB");
1428 PRINT_NXS(31, spd->trfc1_min_msb,
1429 "trfc1_min_msb Min Refresh Recovery Delay Time, MSB ");
1430 PRINT_NXS(32, spd->trfc2_min_lsb,
1431 "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB");
1432 PRINT_NXS(33, spd->trfc2_min_msb,
1433 "trfc2_min_msb Min Refresh Recovery Delay Time, MSB");
1434 PRINT_NXS(34, spd->trfc4_min_lsb,
1435 "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1436 PRINT_NXS(35, spd->trfc4_min_msb,
1437 "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1438 PRINT_NXS(36, spd->tfaw_msb,
1439 "tfaw_msb Upper Nibble for tFAW");
1440 PRINT_NXS(37, spd->tfaw_min,
1441 "tfaw_min tFAW, lsb");
1442 PRINT_NXS(38, spd->trrds_min,
1443 "trrds_min tRRD_Smin, MTB");
1444 PRINT_NXS(39, spd->trrdl_min,
1445 "trrdl_min tRRD_Lmin, MTB");
1446 PRINT_NXS(40, spd->tccdl_min,
1447 "tccdl_min tCCS_Lmin, MTB");
1448
1449 printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */
1450 for (i = 41; i <= 59; i++)
1451 printf("%02x ", spd->res_41[i - 41]);
1452
1453 puts("\n");
1454 printf("%-3d-%3d: ", 60, 77);
1455 for (i = 60; i <= 77; i++)
1456 printf("%02x ", spd->mapping[i - 60]);
1457 puts(" mapping[] Connector to SDRAM bit map\n");
1458
1459 PRINT_NXS(117, spd->fine_tccdl_min,
1460 "fine_tccdl_min Fine offset for tCCD_Lmin");
1461 PRINT_NXS(118, spd->fine_trrdl_min,
1462 "fine_trrdl_min Fine offset for tRRD_Lmin");
1463 PRINT_NXS(119, spd->fine_trrds_min,
1464 "fine_trrds_min Fine offset for tRRD_Smin");
1465 PRINT_NXS(120, spd->fine_trc_min,
1466 "fine_trc_min Fine offset for tRCmin");
1467 PRINT_NXS(121, spd->fine_trp_min,
1468 "fine_trp_min Fine offset for tRPmin");
1469 PRINT_NXS(122, spd->fine_trcd_min,
1470 "fine_trcd_min Fine offset for tRCDmin");
1471 PRINT_NXS(123, spd->fine_taa_min,
1472 "fine_taa_min Fine offset for tAAmin");
1473 PRINT_NXS(124, spd->fine_tck_max,
1474 "fine_tck_max Fine offset for tCKAVGmax");
1475 PRINT_NXS(125, spd->fine_tck_min,
1476 "fine_tck_min Fine offset for tCKAVGmin");
1477
1478 /* CRC: Bytes 126-127 */
1479 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1480
1481 switch (spd->module_type) {
1482 case 0x02: /* UDIMM */
1483 case 0x03: /* SO-DIMM */
1484 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1485 "mod_height (Unbuffered) Module Nominal Height");
1486 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1487 "mod_thickness (Unbuffered) Module Maximum Thickness");
1488 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1489 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1490 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1491 "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM");
1492 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1493 spd->mod_section.unbuffered.crc[1], " Module CRC");
1494 break;
1495 case 0x01: /* RDIMM */
1496 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1497 "mod_height (Registered) Module Nominal Height");
1498 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1499 "mod_thickness (Registered) Module Maximum Thickness");
1500 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1501 "ref_raw_card (Registered) Reference Raw Card Used");
1502 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1503 "modu_attr (Registered) DIMM Module Attributes");
1504 PRINT_NXS(132, spd->mod_section.registered.thermal,
1505 "thermal (Registered) Thermal Heat Spreader Solution");
1506 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1507 "reg_id_lo (Registered) Register Manufacturer ID Code, LSB");
1508 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1509 "reg_id_hi (Registered) Register Manufacturer ID Code, MSB");
1510 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1511 "reg_rev (Registered) Register Revision Number");
1512 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1513 "reg_map (Registered) Address mapping");
1514 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1515 spd->mod_section.registered.crc[1], " Module CRC");
1516 break;
1517 case 0x04: /* LRDIMM */
1518 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1519 "mod_height (Loadreduced) Module Nominal Height");
1520 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1521 "mod_thickness (Loadreduced) Module Maximum Thickness");
1522 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1523 "ref_raw_card (Loadreduced) Reference Raw Card Used");
1524 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1525 "modu_attr (Loadreduced) DIMM Module Attributes");
1526 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1527 "thermal (Loadreduced) Thermal Heat Spreader Solution");
1528 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1529 "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB");
1530 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1531 "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB");
1532 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1533 "reg_rev (Loadreduced) Register Revision Number");
1534 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1535 "reg_map (Loadreduced) Address mapping");
1536 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1537 "reg_drv (Loadreduced) Reg output drive strength");
1538 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1539 "reg_drv_ck (Loadreduced) Reg output drive strength for CK");
1540 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1541 "data_buf_rev (Loadreduced) Data Buffer Revision Numbe");
1542 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1543 "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0");
1544 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1545 "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1");
1546 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1547 "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2");
1548 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1549 "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3");
1550 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1551 "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1552 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1553 "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1554 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1555 "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1556 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1557 "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1558 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1559 "dram_drv (Loadreduced) DRAM Drive Strength");
1560 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1561 "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1562 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1563 "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1564 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1565 "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1566 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1567 "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1568 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1569 "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1570 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1571 "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1572 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1573 spd->mod_section.loadreduced.crc[1],
1574 " Module CRC");
1575 break;
1576 default:
1577 /* Module-specific Section, Unsupported Module Type */
1578 printf("%-3d-%3d: ", 128, 255);
1579
1580 for (i = 128; i <= 255; i++)
1581 printf("%02x", spd->mod_section.uc[i - 60]);
1582
1583 break;
1584 }
1585
1586 /* Unique Module ID: Bytes 320-383 */
1587 PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1588 PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1589 PRINT_NXS(322, spd->mloc, "Mfg Location");
1590 PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1591
1592 printf("%-3d-%3d: ", 325, 328);
1593
1594 for (i = 325; i <= 328; i++)
1595 printf("%02x ", spd->sernum[i - 325]);
1596 printf(" Module Serial Number\n");
1597
1598 printf("%-3d-%3d: ", 329, 348);
1599 for (i = 329; i <= 348; i++)
1600 printf("%02x ", spd->mpart[i - 329]);
1601 printf(" Mfg's Module Part Number\n");
1602
1603 PRINT_NXS(349, spd->mrev, "Module Revision code");
1604 PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1605 PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1606 PRINT_NXS(352, spd->stepping, "DRAM stepping");
1607
1608 printf("%-3d-%3d: ", 353, 381);
1609 for (i = 353; i <= 381; i++)
1610 printf("%02x ", spd->msd[i - 353]);
1611 printf(" Mfg's Specific Data\n");
1612}
1613#endif
1614
1248static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1249{
1250#if defined(CONFIG_SYS_FSL_DDR1)
1251 ddr1_spd_dump(spd);
1252#elif defined(CONFIG_SYS_FSL_DDR2)
1253 ddr2_spd_dump(spd);
1254#elif defined(CONFIG_SYS_FSL_DDR3)
1255 ddr3_spd_dump(spd);
1615static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1616{
1617#if defined(CONFIG_SYS_FSL_DDR1)
1618 ddr1_spd_dump(spd);
1619#elif defined(CONFIG_SYS_FSL_DDR2)
1620 ddr2_spd_dump(spd);
1621#elif defined(CONFIG_SYS_FSL_DDR3)
1622 ddr3_spd_dump(spd);
1623#elif defined(CONFIG_SYS_FSL_DDR4)
1624 ddr4_spd_dump(spd);
1256#endif
1257}
1258
1259static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1260 unsigned int ctrl_mask,
1261 unsigned int dimm_mask,
1262 unsigned int do_mask)
1263{

--- 608 unchanged lines hidden --- 		1625#endif
1626}
1627
1628static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1629 unsigned int ctrl_mask,
1630 unsigned int dimm_mask,
1631 unsigned int do_mask)
1632{

--- 608 unchanged lines hidden ---