zynqmp.c (dcf4cb068e19a7f39e4a295102b247376bd27c95) zynqmp.c (0785dfd8a7b14cb2c99fc1271c865eb2170c620b)
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <netdev.h>
10#include <ahci.h>
11#include <scsi.h>
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <netdev.h>
10#include <ahci.h>
11#include <scsi.h>
12#include <asm/arch/clk.h>
12#include <asm/arch/hardware.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/io.h>
15#include <usb.h>
16#include <dwc3-uboot.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20int board_init(void)
21{
22 printf("EL Level:\tEL%d\n", current_el());
23
24 return 0;
25}
26
27int board_early_init_r(void)
28{
29 u32 val;
30
13#include <asm/arch/hardware.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/io.h>
16#include <usb.h>
17#include <dwc3-uboot.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_init(void)
22{
23 printf("EL Level:\tEL%d\n", current_el());
24
25 return 0;
26}
27
28int board_early_init_r(void)
29{
30 u32 val;
31
31 val = readl(&crlapb_base->timestamp_ref_ctrl);
32 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
33 writel(val, &crlapb_base->timestamp_ref_ctrl);
32 if (current_el() == 3) {
33 val = readl(&crlapb_base->timestamp_ref_ctrl);
34 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
35 writel(val, &crlapb_base->timestamp_ref_ctrl);
34
36
37 /* Program freq register in System counter */
38 writel(zynqmp_get_system_timer_freq(),
39 &iou_scntr_secure->base_frequency_id_register);
40 /* And enable system counter */
41 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
42 &iou_scntr_secure->counter_control_register);
43 }
35 /* Program freq register in System counter and enable system counter */
36 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
37 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
38 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
39 &iou_scntr->counter_control_register);
40
41 return 0;
42}

--- 77 unchanged lines hidden --- 		44 /* Program freq register in System counter and enable system counter */
45 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
46 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
47 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
48 &iou_scntr->counter_control_register);
49
50 return 0;
51}

--- 77 unchanged lines hidden ---