zynqmp.c (b939689c7b87773c44275a578ffc8674a867e39d) zynqmp.c (cb7ea82059069c6509c26b1f705982c6a919a3fe)
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>

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46{
47 return 0;
48}
49
50void reset_cpu(ulong addr)
51{
52}
53
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>

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46{
47 return 0;
48}
49
50void reset_cpu(ulong addr)
51{
52}
53
54int board_eth_init(bd_t *bis)
55{
56 u32 ret = 0;
57
58#if defined(CONFIG_ZYNQ_GEM)
59# if defined(CONFIG_ZYNQ_GEM0)
60 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
61 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
62# endif
63# if defined(CONFIG_ZYNQ_GEM1)
64 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
65 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
66# endif
67# if defined(CONFIG_ZYNQ_GEM2)
68 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
69 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
70# endif
71# if defined(CONFIG_ZYNQ_GEM3)
72 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
73 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
74# endif
75#endif
76 return ret;
77}
78
54#ifdef CONFIG_CMD_MMC
55int board_mmc_init(bd_t *bd)
56{
57 int ret = 0;
58
59 u32 ver = zynqmp_get_silicon_version();
60
61 if (ver != ZYNQMP_CSU_VERSION_VELOCE) {

--- 34 unchanged lines hidden --- 		79#ifdef CONFIG_CMD_MMC
80int board_mmc_init(bd_t *bd)
81{
82 int ret = 0;
83
84 u32 ver = zynqmp_get_silicon_version();
85
86 if (ver != ZYNQMP_CSU_VERSION_VELOCE) {

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