zynqmp.c (8ebdf9efad9337a4bec65b8b39a48c0c7b39161a) zynqmp.c (494fffe70d6ebb4e4bffa4dc0a55df6b2b9a58d9)
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>

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23DECLARE_GLOBAL_DATA_PTR;
24
25#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
28
29static const struct {
30 u32 id;
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>

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23DECLARE_GLOBAL_DATA_PTR;
24
25#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
28
29static const struct {
30 u32 id;
31 u32 ver;
31 char *name;
32} zynqmp_devices[] = {
33 {
34 .id = 0x10,
35 .name = "3eg",
36 },
37 {
32 char *name;
33} zynqmp_devices[] = {
34 {
35 .id = 0x10,
36 .name = "3eg",
37 },
38 {
39 .id = 0x10,
40 .ver = 0x2c,
41 .name = "3cg",
42 },
43 {
38 .id = 0x11,
39 .name = "2eg",
40 },
41 {
44 .id = 0x11,
45 .name = "2eg",
46 },
47 {
48 .id = 0x11,
49 .ver = 0x2c,
50 .name = "2cg",
51 },
52 {
42 .id = 0x20,
43 .name = "5ev",
44 },
45 {
53 .id = 0x20,
54 .name = "5ev",
55 },
56 {
57 .id = 0x20,
58 .ver = 0x100,
59 .name = "5eg",
60 },
61 {
62 .id = 0x20,
63 .ver = 0x12c,
64 .name = "5cg",
65 },
66 {
46 .id = 0x21,
47 .name = "4ev",
48 },
49 {
67 .id = 0x21,
68 .name = "4ev",
69 },
70 {
71 .id = 0x21,
72 .ver = 0x100,
73 .name = "4eg",
74 },
75 {
76 .id = 0x21,
77 .ver = 0x12c,
78 .name = "4cg",
79 },
80 {
50 .id = 0x30,
51 .name = "7ev",
52 },
53 {
81 .id = 0x30,
82 .name = "7ev",
83 },
84 {
85 .id = 0x30,
86 .ver = 0x100,
87 .name = "7eg",
88 },
89 {
90 .id = 0x30,
91 .ver = 0x12c,
92 .name = "7cg",
93 },
94 {
54 .id = 0x38,
55 .name = "9eg",
56 },
57 {
95 .id = 0x38,
96 .name = "9eg",
97 },
98 {
99 .id = 0x38,
100 .ver = 0x2c,
101 .name = "9cg",
102 },
103 {
58 .id = 0x39,
59 .name = "6eg",
60 },
61 {
104 .id = 0x39,
105 .name = "6eg",
106 },
107 {
108 .id = 0x39,
109 .ver = 0x2c,
110 .name = "6cg",
111 },
112 {
62 .id = 0x40,
63 .name = "11eg",
64 },
113 .id = 0x40,
114 .name = "11eg",
115 },
116 { /* For testing purpose only */
117 .id = 0x50,
118 .ver = 0x2c,
119 .name = "15cg",
120 },
65 {
66 .id = 0x50,
67 .name = "15eg",
68 },
69 {
70 .id = 0x58,
71 .name = "19eg",
72 },

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90
91 smc_call(&regs);
92
93 /*
94 * SMC returns:
95 * regs[0][31:0] = status of the operation
96 * regs[0][63:32] = CSU.IDCODE register
97 * regs[1][31:0] = CSU.version register
121 {
122 .id = 0x50,
123 .name = "15eg",
124 },
125 {
126 .id = 0x58,
127 .name = "19eg",
128 },

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146
147 smc_call(&regs);
148
149 /*
150 * SMC returns:
151 * regs[0][31:0] = status of the operation
152 * regs[0][63:32] = CSU.IDCODE register
153 * regs[1][31:0] = CSU.version register
154 * regs[1][63:32] = CSU.IDCODE2 register
98 */
99 switch (id) {
100 case IDCODE:
101 regs.regs[0] = upper_32_bits(regs.regs[0]);
102 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
103 ZYNQMP_CSU_IDCODE_SVD_MASK;
104 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
105 val = regs.regs[0];
106 break;
107 case VERSION:
108 regs.regs[1] = lower_32_bits(regs.regs[1]);
109 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
110 val = regs.regs[1];
111 break;
155 */
156 switch (id) {
157 case IDCODE:
158 regs.regs[0] = upper_32_bits(regs.regs[0]);
159 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
160 ZYNQMP_CSU_IDCODE_SVD_MASK;
161 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
162 val = regs.regs[0];
163 break;
164 case VERSION:
165 regs.regs[1] = lower_32_bits(regs.regs[1]);
166 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
167 val = regs.regs[1];
168 break;
169 case IDCODE2:
170 regs.regs[1] = lower_32_bits(regs.regs[1]);
171 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
172 val = regs.regs[1];
173 break;
112 default:
113 printf("%s, Invalid Req:0x%x\n", __func__, id);
114 }
115 } else {
116 switch (id) {
117 case IDCODE:
118 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
119 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |

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131
132 return val;
133}
134
135#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
136 !defined(CONFIG_SPL_BUILD)
137static char *zynqmp_get_silicon_idcode_name(void)
138{
174 default:
175 printf("%s, Invalid Req:0x%x\n", __func__, id);
176 }
177 } else {
178 switch (id) {
179 case IDCODE:
180 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
181 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |

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193
194 return val;
195}
196
197#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
198 !defined(CONFIG_SPL_BUILD)
199static char *zynqmp_get_silicon_idcode_name(void)
200{
139 u32 i, id;
201 u32 i, id, ver;
140
141 id = chip_id(IDCODE);
202
203 id = chip_id(IDCODE);
204 ver = chip_id(IDCODE2);
205
142 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
206 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
143 if (zynqmp_devices[i].id == id)
207 if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
144 return zynqmp_devices[i].name;
145 }
146 return "unknown";
147}
148#endif
149
150int board_early_init_f(void)
151{

--- 226 unchanged lines hidden --- 		208 return zynqmp_devices[i].name;
209 }
210 return "unknown";
211}
212#endif
213
214int board_early_init_f(void)
215{

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