| zynqmp.c (4490e013ee4f2a4b9b6ca9224221fed2788b6940) | zynqmp.c (0678941ae54b3f1bbd8024c8d74fb282f0c1b590) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7#include <common.h> 8#include <sata.h> --- 391 unchanged lines hidden (view full) --- 400 ret = EINVAL; 401 } 402 return ret; 403} 404 405#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 406int dram_init_banksize(void) 407{ | 1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7#include <common.h> 8#include <sata.h> --- 391 unchanged lines hidden (view full) --- 400 ret = EINVAL; 401 } 402 return ret; 403} 404 405#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 406int dram_init_banksize(void) 407{ |
| 408 return fdtdec_setup_memory_banksize(); | 408 int ret; 409 410 ret = fdtdec_setup_memory_banksize(); 411 if (ret) 412 return ret; 413 414 mem_map_fill(); 415 416 return 0; |
| 409} 410 411int dram_init(void) 412{ 413 if (fdtdec_setup_memory_size() != 0) 414 return -EINVAL; 415 416 return 0; 417} 418#else | 417} 418 419int dram_init(void) 420{ 421 if (fdtdec_setup_memory_size() != 0) 422 return -EINVAL; 423 424 return 0; 425} 426#else |
| 427int dram_init_banksize(void) 428{ 429#if defined(CONFIG_NR_DRAM_BANKS) 430 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 431 gd->bd->bi_dram[0].size = get_effective_memsize(); 432#endif 433 434 mem_map_fill(); 435 436 return 0; 437} 438 |
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| 419int dram_init(void) 420{ 421 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 422 CONFIG_SYS_SDRAM_SIZE); 423 424 return 0; 425} 426#endif --- 150 unchanged lines hidden --- | 439int dram_init(void) 440{ 441 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 442 CONFIG_SYS_SDRAM_SIZE); 443 444 return 0; 445} 446#endif --- 150 unchanged lines hidden --- |