board.c (d0423c44f1acc68da10da8c16af4d82016479d7b) board.c (fb771793bd5daa8b4dcf5664ea0cf02b1ca2ae0f)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7#include <common.h>
8#include <fdtdec.h>

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16{
17 printf("EL Level:\tEL%d\n", current_el());
18
19 return 0;
20}
21
22int board_early_init_r(void)
23{
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7#include <common.h>
8#include <fdtdec.h>

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16{
17 printf("EL Level:\tEL%d\n", current_el());
18
19 return 0;
20}
21
22int board_early_init_r(void)
23{
24 if (current_el() == 3) {
25 u32 val;
24 u32 val;
26
25
27 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
28 (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
29 &crlapb_base->iou_switch_ctrl);
26 if (current_el() != 3)
27 return 0;
30
28
31 /* Global timer init - Program time stamp reference clk */
32 val = readl(&crlapb_base->timestamp_ref_ctrl);
33 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
34 writel(val, &crlapb_base->timestamp_ref_ctrl);
29 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
30 (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
31 &crlapb_base->iou_switch_ctrl);
35
32
36 debug("ref ctrl 0x%x\n",
37 readl(&crlapb_base->timestamp_ref_ctrl));
33 /* Global timer init - Program time stamp reference clk */
34 val = readl(&crlapb_base->timestamp_ref_ctrl);
35 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
36 writel(val, &crlapb_base->timestamp_ref_ctrl);
38
37
39 /* Clear reset of timestamp reg */
40 writel(0, &crlapb_base->rst_timestamp);
38 debug("ref ctrl 0x%x\n",
39 readl(&crlapb_base->timestamp_ref_ctrl));
41
40
42 /*
43 * Program freq register in System counter and
44 * enable system counter.
45 */
46 writel(COUNTER_FREQUENCY,
47 &iou_scntr_secure->base_frequency_id_register);
41 /* Clear reset of timestamp reg */
42 writel(0, &crlapb_base->rst_timestamp);
48
43
49 debug("counter val 0x%x\n",
50 readl(&iou_scntr_secure->base_frequency_id_register));
44 /*
45 * Program freq register in System counter and
46 * enable system counter.
47 */
48 writel(COUNTER_FREQUENCY,
49 &iou_scntr_secure->base_frequency_id_register);
51
50
52 writel(IOU_SCNTRS_CONTROL_EN,
53 &iou_scntr_secure->counter_control_register);
51 debug("counter val 0x%x\n",
52 readl(&iou_scntr_secure->base_frequency_id_register));
54
53
55 debug("scntrs control 0x%x\n",
56 readl(&iou_scntr_secure->counter_control_register));
57 debug("timer 0x%llx\n", get_ticks());
58 debug("timer 0x%llx\n", get_ticks());
59 }
54 writel(IOU_SCNTRS_CONTROL_EN,
55 &iou_scntr_secure->counter_control_register);
60
56
57 debug("scntrs control 0x%x\n",
58 readl(&iou_scntr_secure->counter_control_register));
59 debug("timer 0x%llx\n", get_ticks());
60 debug("timer 0x%llx\n", get_ticks());
61
61 return 0;
62}
63
64int dram_init_banksize(void)
65{
66 fdtdec_setup_memory_banksize();
67
68 return 0;

--- 13 unchanged lines hidden --- 		62 return 0;
63}
64
65int dram_init_banksize(void)
66{
67 fdtdec_setup_memory_banksize();
68
69 return 0;

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