evm.c (fede94298049fe243eaed08a10db67fe9bcb17a2) evm.c (ba39608147c797cffb266579b5791649f0f8e60c)
1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>

--- 279 unchanged lines hidden (view full) ---

288 case DRA762_ES1_0:
289 if (emif_nr == 1)
290 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
291 else
292 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
293 break;
294 case DRA722_ES1_0:
295 case DRA722_ES2_0:
1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>

--- 279 unchanged lines hidden (view full) ---

288 case DRA762_ES1_0:
289 if (emif_nr == 1)
290 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
291 else
292 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
293 break;
294 case DRA722_ES1_0:
295 case DRA722_ES2_0:
296 case DRA722_ES2_1:
296 if (ram_size < CONFIG_MAX_MEM_MAPPED)
297 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
298 else
299 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
300 break;
301 default:
302 *regs = &emif1_ddr3_532_mhz_1cs;
303 }

--- 48 unchanged lines hidden (view full) ---

352 case DRA752_ES2_0:
353 if (ram_size > CONFIG_MAX_MEM_MAPPED)
354 *dmm_lisa_regs = &lisa_map_dra7_2GB;
355 else
356 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
357 break;
358 case DRA722_ES1_0:
359 case DRA722_ES2_0:
297 if (ram_size < CONFIG_MAX_MEM_MAPPED)
298 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
299 else
300 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
301 break;
302 default:
303 *regs = &emif1_ddr3_532_mhz_1cs;
304 }

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353 case DRA752_ES2_0:
354 if (ram_size > CONFIG_MAX_MEM_MAPPED)
355 *dmm_lisa_regs = &lisa_map_dra7_2GB;
356 else
357 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
358 break;
359 case DRA722_ES1_0:
360 case DRA722_ES2_0:
361 case DRA722_ES2_1:
360 default:
361 if (ram_size < CONFIG_MAX_MEM_MAPPED)
362 *dmm_lisa_regs = &lisa_map_2G_x_2;
363 else
364 *dmm_lisa_regs = &lisa_map_2G_x_4;
365 break;
366 }
367}

--- 382 unchanged lines hidden (view full) ---

750 struct pad_conf_entry const *pads, *delta_pads = NULL;
751 struct iodelay_cfg_entry const *iodelay;
752 int npads, niodelays, delta_npads = 0;
753 int ret;
754
755 switch (omap_revision()) {
756 case DRA722_ES1_0:
757 case DRA722_ES2_0:
362 default:
363 if (ram_size < CONFIG_MAX_MEM_MAPPED)
364 *dmm_lisa_regs = &lisa_map_2G_x_2;
365 else
366 *dmm_lisa_regs = &lisa_map_2G_x_4;
367 break;
368 }
369}

--- 382 unchanged lines hidden (view full) ---

752 struct pad_conf_entry const *pads, *delta_pads = NULL;
753 struct iodelay_cfg_entry const *iodelay;
754 int npads, niodelays, delta_npads = 0;
755 int ret;
756
757 switch (omap_revision()) {
758 case DRA722_ES1_0:
759 case DRA722_ES2_0:
760 case DRA722_ES2_1:
758 pads = dra72x_core_padconf_array_common;
759 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
760 if (board_is_dra71x_evm()) {
761 pads = dra71x_core_padconf_array;
762 npads = ARRAY_SIZE(dra71x_core_padconf_array);
763 iodelay = dra71_iodelay_cfg_array;
764 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
765 } else if (board_is_dra72x_revc_or_later()) {

--- 375 unchanged lines hidden --- 		761 pads = dra72x_core_padconf_array_common;
762 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
763 if (board_is_dra71x_evm()) {
764 pads = dra71x_core_padconf_array;
765 npads = ARRAY_SIZE(dra71x_core_padconf_array);
766 iodelay = dra71_iodelay_cfg_array;
767 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
768 } else if (board_is_dra72x_revc_or_later()) {

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