evm.c (e36edcec0a2491d1e31ddb9d82d77b9763e9aef0) evm.c (941f2fcc5bc66aceb993032a05641248eb092e11)
1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>

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280 case 2:
281 if (ram_size > CONFIG_MAX_MEM_MAPPED)
282 *regs = &emif2_ddr3_532_mhz_1cs_2G;
283 else
284 *regs = &emif2_ddr3_532_mhz_1cs;
285 break;
286 }
287 break;
1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>

--- 271 unchanged lines hidden (view full) ---

280 case 2:
281 if (ram_size > CONFIG_MAX_MEM_MAPPED)
282 *regs = &emif2_ddr3_532_mhz_1cs_2G;
283 else
284 *regs = &emif2_ddr3_532_mhz_1cs;
285 break;
286 }
287 break;
288 case DRA762_ABZ_ES1_0:
289 case DRA762_ACD_ES1_0:
288 case DRA762_ES1_0:
289 if (emif_nr == 1)
290 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
291 else
292 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
293 break;
294 case DRA722_ES1_0:
295 case DRA722_ES2_0:

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342
343void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
344{
345 u64 ram_size;
346
347 ram_size = board_ti_get_emif_size();
348
349 switch (omap_revision()) {
290 case DRA762_ES1_0:
291 if (emif_nr == 1)
292 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
293 else
294 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
295 break;
296 case DRA722_ES1_0:
297 case DRA722_ES2_0:

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344
345void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
346{
347 u64 ram_size;
348
349 ram_size = board_ti_get_emif_size();
350
351 switch (omap_revision()) {
352 case DRA762_ABZ_ES1_0:
353 case DRA762_ACD_ES1_0:
350 case DRA762_ES1_0:
351 case DRA752_ES1_0:
352 case DRA752_ES1_1:
353 case DRA752_ES2_0:
354 if (ram_size > CONFIG_MAX_MEM_MAPPED)
355 *dmm_lisa_regs = &lisa_map_dra7_2GB;
356 else
357 *dmm_lisa_regs = &lisa_map_dra7_1536MB;

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650
651 if (is_dra72x()) {
652 if (board_is_dra72x_revc_or_later())
653 name = "dra72x-revc";
654 else if (board_is_dra71x_evm())
655 name = "dra71x";
656 else
657 name = "dra72x";
354 case DRA762_ES1_0:
355 case DRA752_ES1_0:
356 case DRA752_ES1_1:
357 case DRA752_ES2_0:
358 if (ram_size > CONFIG_MAX_MEM_MAPPED)
359 *dmm_lisa_regs = &lisa_map_dra7_2GB;
360 else
361 *dmm_lisa_regs = &lisa_map_dra7_1536MB;

--- 292 unchanged lines hidden (view full) ---

654
655 if (is_dra72x()) {
656 if (board_is_dra72x_revc_or_later())
657 name = "dra72x-revc";
658 else if (board_is_dra71x_evm())
659 name = "dra71x";
660 else
661 name = "dra72x";
658 } else if (is_dra76x()) {
659 name = "dra76x";
662 } else if (is_dra76x_abz()) {
663 name = "dra76x_abz";
664 } else if (is_dra76x_acd()) {
665 name = "dra76x_acd";
660 } else {
661 name = "dra7xx";
662 }
663
664 set_board_info_env(name);
665
666 /*
667 * Default FIT boot on HS devices. Non FIT images are not allowed

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788 break;
789 case DRA752_ES1_0:
790 case DRA752_ES1_1:
791 pads = dra74x_core_padconf_array;
792 npads = ARRAY_SIZE(dra74x_core_padconf_array);
793 iodelay = dra742_es1_1_iodelay_cfg_array;
794 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
795 break;
666 } else {
667 name = "dra7xx";
668 }
669
670 set_board_info_env(name);
671
672 /*
673 * Default FIT boot on HS devices. Non FIT images are not allowed

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794 break;
795 case DRA752_ES1_0:
796 case DRA752_ES1_1:
797 pads = dra74x_core_padconf_array;
798 npads = ARRAY_SIZE(dra74x_core_padconf_array);
799 iodelay = dra742_es1_1_iodelay_cfg_array;
800 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
801 break;
802 case DRA762_ACD_ES1_0:
796 case DRA762_ES1_0:
797 pads = dra76x_core_padconf_array;
798 npads = ARRAY_SIZE(dra76x_core_padconf_array);
799 iodelay = dra76x_es1_0_iodelay_cfg_array;
800 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
801 break;
802 default:
803 case DRA752_ES2_0:
803 case DRA762_ES1_0:
804 pads = dra76x_core_padconf_array;
805 npads = ARRAY_SIZE(dra76x_core_padconf_array);
806 iodelay = dra76x_es1_0_iodelay_cfg_array;
807 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
808 break;
809 default:
810 case DRA752_ES2_0:
811 case DRA762_ABZ_ES1_0:
804 pads = dra74x_core_padconf_array;
805 npads = ARRAY_SIZE(dra74x_core_padconf_array);
806 iodelay = dra742_es2_0_iodelay_cfg_array;
807 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
808 /* Setup port1 and port2 for rgmii with 'no-id' mode */
809 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
810 RGMII1_ID_MODE_N_MASK);
811 break;

--- 313 unchanged lines hidden (view full) ---

1125 if (!strcmp(name, "dra71-evm"))
1126 return 0;
1127 }else if(board_is_dra72x_revc_or_later()) {
1128 if (!strcmp(name, "dra72-evm-revc"))
1129 return 0;
1130 } else if (!strcmp(name, "dra72-evm")) {
1131 return 0;
1132 }
812 pads = dra74x_core_padconf_array;
813 npads = ARRAY_SIZE(dra74x_core_padconf_array);
814 iodelay = dra742_es2_0_iodelay_cfg_array;
815 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
816 /* Setup port1 and port2 for rgmii with 'no-id' mode */
817 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
818 RGMII1_ID_MODE_N_MASK);
819 break;

--- 313 unchanged lines hidden (view full) ---

1133 if (!strcmp(name, "dra71-evm"))
1134 return 0;
1135 }else if(board_is_dra72x_revc_or_later()) {
1136 if (!strcmp(name, "dra72-evm-revc"))
1137 return 0;
1138 } else if (!strcmp(name, "dra72-evm")) {
1139 return 0;
1140 }
1133 } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
1141 } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
1134 return 0;
1142 return 0;
1135 } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
1143 } else if (!is_dra72x() && !is_dra76x_acd() &&
1144 !strcmp(name, "dra7-evm")) {
1136 return 0;
1137 }
1138
1139 return -1;
1140}
1141#endif
1142
1143#ifdef CONFIG_TI_SECURE_DEVICE

--- 12 unchanged lines hidden --- 		1145 return 0;
1146 }
1147
1148 return -1;
1149}
1150#endif
1151
1152#ifdef CONFIG_TI_SECURE_DEVICE

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