evm.c (8b485ba12b0defa0c4ed3559789250238f8331a8) evm.c (b1e26e3bfb1d53d4fd713a2a5f11b7ddf2bcaeec)
1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>

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18#include "mux_data.h"
19
20#ifdef CONFIG_USB_EHCI
21#include <usb.h>
22#include <asm/arch/ehci.h>
23#include <asm/ehci-omap.h>
24#endif
25
1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>

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18#include "mux_data.h"
19
20#ifdef CONFIG_USB_EHCI
21#include <usb.h>
22#include <asm/arch/ehci.h>
23#include <asm/ehci-omap.h>
24#endif
25
26#ifdef CONFIG_DRIVER_TI_CPSW
27#include <cpsw.h>
28#endif
29
26DECLARE_GLOBAL_DATA_PTR;
27
28const struct omap_sysinfo sysinfo = {
29 "Board: DRA7xx\n"
30};
31
30DECLARE_GLOBAL_DATA_PTR;
31
32const struct omap_sysinfo sysinfo = {
33 "Board: DRA7xx\n"
34};
35
36/*
37 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
38 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
39 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
40 * essentially need to counteract the DRA7xx internal delay, and we do this
41 * by delaying the control and data lines. If not using this PHY, you probably
42 * don't need to do this stuff!
43 */
44static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
45{
46 int i = 0;
47 u32 reg_val;
48 u32 delta;
49 u32 coarse;
50 u32 fine;
51
52 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
53
54 while(io_dly[i].addr) {
55 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
56 io_dly[i].addr);
57 delta = io_dly[i].dly;
58 reg_val = readl(io_dly[i].addr) & 0x3ff;
59 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
60 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
61 fine = (reg_val & 0x1F) + (delta & 0x1F);
62 fine = (fine > 0x1F) ? (0x1F) : (fine);
63 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
64 CFG_IO_DELAY_LOCK_MASK |
65 ((coarse << 5) | (fine));
66 writel(reg_val, io_dly[i].addr);
67 i++;
68 }
69
70 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
71}
72
32/**
33 * @brief board_init
34 *
35 * @return 0
36 */
37int board_init(void)
38{
39 gpmc_init();
40 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
41
42 return 0;
43}
44
73/**
74 * @brief board_init
75 *
76 * @return 0
77 */
78int board_init(void)
79{
80 gpmc_init();
81 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
82
83 return 0;
84}
85
45int board_eth_init(bd_t *bis)
46{
47 return 0;
48}
49
50/**
51 * @brief misc_init_r - Configure EVM board specific configurations
52 * such as power configurations, ethernet initialization as phase2 of
53 * boot sequence
54 *
55 * @return 0
56 */
57int misc_init_r(void)

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80#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
81int board_mmc_init(bd_t *bis)
82{
83 omap_mmc_init(0, 0, 0, -1, -1);
84 omap_mmc_init(1, 0, 0, -1, -1);
85 return 0;
86}
87#endif
86/**
87 * @brief misc_init_r - Configure EVM board specific configurations
88 * such as power configurations, ethernet initialization as phase2 of
89 * boot sequence
90 *
91 * @return 0
92 */
93int misc_init_r(void)

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116#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
117int board_mmc_init(bd_t *bis)
118{
119 omap_mmc_init(0, 0, 0, -1, -1);
120 omap_mmc_init(1, 0, 0, -1, -1);
121 return 0;
122}
123#endif
124
125#ifdef CONFIG_DRIVER_TI_CPSW
126
127/* Delay value to add to calibrated value */
128#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
129#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
130#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
131#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
132#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
133#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
134#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
135#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
136#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
137#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
138
139static void cpsw_control(int enabled)
140{
141 /* VTP can be added here */
142
143 return;
144}
145
146static struct cpsw_slave_data cpsw_slaves[] = {
147 {
148 .slave_reg_ofs = 0x208,
149 .sliver_reg_ofs = 0xd80,
150 .phy_id = 0,
151 },
152 {
153 .slave_reg_ofs = 0x308,
154 .sliver_reg_ofs = 0xdc0,
155 .phy_id = 1,
156 },
157};
158
159static struct cpsw_platform_data cpsw_data = {
160 .mdio_base = CPSW_MDIO_BASE,
161 .cpsw_base = CPSW_BASE,
162 .mdio_div = 0xff,
163 .channels = 8,
164 .cpdma_reg_ofs = 0x800,
165 .slaves = 1,
166 .slave_data = cpsw_slaves,
167 .ale_reg_ofs = 0xd00,
168 .ale_entries = 1024,
169 .host_port_reg_ofs = 0x108,
170 .hw_stats_reg_ofs = 0x900,
171 .bd_ram_ofs = 0x2000,
172 .mac_control = (1 << 5),
173 .control = cpsw_control,
174 .host_port_num = 0,
175 .version = CPSW_CTRL_VERSION_2,
176};
177
178int board_eth_init(bd_t *bis)
179{
180 int ret;
181 uint8_t mac_addr[6];
182 uint32_t mac_hi, mac_lo;
183 uint32_t ctrl_val;
184 const struct io_delay io_dly[] = {
185 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
186 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
187 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
188 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
189 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
190 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
191 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
192 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
193 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
194 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
195 {0}
196 };
197
198 /* Adjust IO delay for RGMII tx path */
199 dra7xx_adj_io_delay(io_dly);
200
201 /* try reading mac address from efuse */
202 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
203 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
204 mac_addr[0] = mac_hi & 0xFF;
205 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
206 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
207 mac_addr[3] = mac_lo & 0xFF;
208 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
209 mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
210
211 if (!getenv("ethaddr")) {
212 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
213
214 if (is_valid_ether_addr(mac_addr))
215 eth_setenv_enetaddr("ethaddr", mac_addr);
216 }
217 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
218 ctrl_val |= 0x22;
219 writel(ctrl_val, (*ctrl)->control_core_control_io1);
220
221 ret = cpsw_register(&cpsw_data);
222 if (ret < 0)
223 printf("Error %d registering CPSW switch\n", ret);
224
225 return ret;
226}
227#endif