| mx6cuboxi.c (6d97dc10a81062a787fcf5e5df7b88d1ea122a64) | mx6cuboxi.c (f2ff834365296151b24bf8617f1f6dd070bdce9e) |
|---|---|
| 1/* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> 7 * 8 * Based on SPL code from Solidrun tree, which is: --- 601 unchanged lines hidden (view full) --- 610 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 611 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 612 .walat = 1, /* Write additional latency */ 613 .ralat = 5, /* Read additional latency */ 614 .mif3_mode = 3, /* Command prediction working mode */ 615 .bi_on = 1, /* Bank interleaving enabled */ 616 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 617 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ | 1/* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> 7 * 8 * Based on SPL code from Solidrun tree, which is: --- 601 unchanged lines hidden (view full) --- 610 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 611 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 612 .walat = 1, /* Write additional latency */ 613 .ralat = 5, /* Read additional latency */ 614 .mif3_mode = 3, /* Command prediction working mode */ 615 .bi_on = 1, /* Bank interleaving enabled */ 616 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 617 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| 618 .ddr_type = DDR_TYPE_DDR3, |
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| 618 }; 619 620 if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) 621 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); 622 else 623 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); 624 625 if (is_cpu_type(MXC_CPU_MX6D)) --- 39 unchanged lines hidden --- | 619 }; 620 621 if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) 622 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); 623 else 624 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); 625 626 if (is_cpu_type(MXC_CPU_MX6D)) --- 39 unchanged lines hidden --- |