ddr.c (52c411805c090999f015df8bdf8016fb684746d0) ddr.c (088454cde245b4d431ce0181be8b3cbceea059d6)
1/*
2 * Copyright (C) 2016 Imagination Technologies
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8
9#include <asm/io.h>
10
11#include "boston-regs.h"
12
1/*
2 * Copyright (C) 2016 Imagination Technologies
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8
9#include <asm/io.h>
10
11#include "boston-regs.h"
12
13phys_size_t initdram(void)
13DECLARE_GLOBAL_DATA_PTR;
14
15int initdram(void)
14{
15 u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
16
16{
17 u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
18
17 return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
19 gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) <<
20 30;
21
22 return 0;
18}
19
20ulong board_get_usable_ram_top(ulong total_size)
21{
22 DECLARE_GLOBAL_DATA_PTR;
23
24 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
25 /* 2GB wrapped around to 0 */
26 return CKSEG0ADDR(256 << 20);
27 }
28
29 return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
30}
23}
24
25ulong board_get_usable_ram_top(ulong total_size)
26{
27 DECLARE_GLOBAL_DATA_PTR;
28
29 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
30 /* 2GB wrapped around to 0 */
31 return CKSEG0ADDR(256 << 20);
32 }
33
34 return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
35}