ids8313.c (52c411805c090999f015df8bdf8016fb684746d0) ids8313.c (088454cde245b4d431ce0181be8b3cbceea059d6)
1/*
2 * (C) Copyright 2013
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * ids8313.c - ids8313 board support.
8 *

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114 if (size_01 > size_02)
115 msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
116 else
117 msize = size_02;
118
119 return msize;
120}
121
1/*
2 * (C) Copyright 2013
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * ids8313.c - ids8313 board support.
8 *

--- 105 unchanged lines hidden (view full) ---

114 if (size_01 > size_02)
115 msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
116 else
117 msize = size_02;
118
119 return msize;
120}
121
122phys_size_t initdram(void)
122int initdram(void)
123{
124 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
125 fsl_lbc_t *lbc = &im->im_lbc;
126 u32 msize = 0;
127
128 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
123{
124 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
125 fsl_lbc_t *lbc = &im->im_lbc;
126 u32 msize = 0;
127
128 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
129 return -1;
129 return -ENXIO;
130
131 msize = setup_sdram();
132
133 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
134 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
135 sync();
136
130
131 msize = setup_sdram();
132
133 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
134 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
135 sync();
136
137 return msize;
137 gd->ram_size = msize;
138
139 return 0;
138}
139
140#if defined(CONFIG_OF_BOARD_SETUP)
141int ft_board_setup(void *blob, bd_t *bd)
142{
143 ft_cpu_setup(blob, bd);
144
145 return 0;

--- 65 unchanged lines hidden --- 		140}
141
142#if defined(CONFIG_OF_BOARD_SETUP)
143int ft_board_setup(void *blob, bd_t *bd)
144{
145 ft_cpu_setup(blob, bd);
146
147 return 0;

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