sdram.c (52c411805c090999f015df8bdf8016fb684746d0) sdram.c (088454cde245b4d431ce0181be8b3cbceea059d6)
1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
8 *

--- 52 unchanged lines hidden (view full) ---

61
62 /* enable DDR controller */
63 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
64 sync();
65
66 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
67}
68
1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
8 *

--- 52 unchanged lines hidden (view full) ---

61
62 /* enable DDR controller */
63 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
64 sync();
65
66 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
67}
68
69phys_size_t initdram(void)
69int initdram(void)
70{
71 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
72 u32 msize;
73
74 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
70{
71 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
72 u32 msize;
73
74 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
75 return -1;
75 return -ENXIO;
76
77 /* DDR SDRAM */
78 msize = fixed_sdram();
79
80 /* return total bus SDRAM size(bytes) -- DDR */
76
77 /* DDR SDRAM */
78 msize = fixed_sdram();
79
80 /* return total bus SDRAM size(bytes) -- DDR */
81 return msize;
81 gd->ram_size = msize;
82
83 return 0;
82}
84}