mx6sabresd.c (7a1af7a79bd79ded6a78d0c1afdbc3353669e313) mx6sabresd.c (f2ff834365296151b24bf8617f1f6dd070bdce9e)
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8

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819 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
820 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
821 .walat = 1, /* Write additional latency */
822 .ralat = 5, /* Read additional latency */
823 .mif3_mode = 3, /* Command prediction working mode */
824 .bi_on = 1, /* Bank interleaving enabled */
825 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
826 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8

--- 810 unchanged lines hidden (view full) ---

819 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
820 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
821 .walat = 1, /* Write additional latency */
822 .ralat = 5, /* Read additional latency */
823 .mif3_mode = 3, /* Command prediction working mode */
824 .bi_on = 1, /* Bank interleaving enabled */
825 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
826 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
827 .ddr_type = DDR_TYPE_DDR3,
827 };
828
829 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
830 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
831}
832
833void board_init_f(ulong dummy)
834{

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829
830 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
831 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
832}
833
834void board_init_f(ulong dummy)
835{

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