mpc8544ds.c (e1ccf97c5d7651664d37c0c5aa243874b8851b2d) mpc8544ds.c (063c12633d5ad74d52152d9c358e715475e17629)
1/*
2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

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28#include <asm/immap_85xx.h>
29#include <asm/fsl_pci.h>
30#include <asm/fsl_ddr_sdram.h>
31#include <asm/fsl_serdes.h>
32#include <asm/io.h>
33#include <miiphy.h>
34#include <libfdt.h>
35#include <fdt_support.h>
1/*
2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

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28#include <asm/immap_85xx.h>
29#include <asm/fsl_pci.h>
30#include <asm/fsl_ddr_sdram.h>
31#include <asm/fsl_serdes.h>
32#include <asm/io.h>
33#include <miiphy.h>
34#include <libfdt.h>
35#include <fdt_support.h>
36#include <fsl_mdio.h>
36#include <tsec.h>
37#include <netdev.h>
38
39#include "../common/sgmii_riser.h"
40
41int checkboard (void)
42{
43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

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243 case 7:
244 val = 166666666;
245 break;
246 }
247
248 return val;
249}
250
37#include <tsec.h>
38#include <netdev.h>
39
40#include "../common/sgmii_riser.h"
41
42int checkboard (void)
43{
44 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

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244 case 7:
245 val = 166666666;
246 break;
247 }
248
249 return val;
250}
251
252
253#define MIIM_CIS8204_SLED_CON 0x1b
254#define MIIM_CIS8204_SLEDCON_INIT 0x1115
255/*
256 * Hack to write all 4 PHYs with the LED values
257 */
258int board_phy_config(struct phy_device *phydev)
259{
260 static int do_once;
261 uint phyid;
262 struct mii_dev *bus = phydev->bus;
263
264 if (do_once)
265 return 0;
266
267 for (phyid = 0; phyid < 4; phyid++)
268 bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
269 MIIM_CIS8204_SLEDCON_INIT);
270
271 do_once = 1;
272
273 return 0;
274}
275
276
251int board_eth_init(bd_t *bis)
252{
253#ifdef CONFIG_TSEC_ENET
277int board_eth_init(bd_t *bis)
278{
279#ifdef CONFIG_TSEC_ENET
280 struct fsl_pq_mdio_info mdio_info;
254 struct tsec_info_struct tsec_info[2];
255 int num = 0;
256
257#ifdef CONFIG_TSEC1
258 SET_STD_TSEC_INFO(tsec_info[num], 1);
259 if (is_serdes_configured(SGMII_TSEC1)) {
260 puts("eTSEC1 is in sgmii mode.\n");
261 tsec_info[num].flags |= TSEC_SGMII;

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277 return 0;
278 }
279
280 if (is_serdes_configured(SGMII_TSEC1) ||
281 is_serdes_configured(SGMII_TSEC3)) {
282 fsl_sgmii_riser_init(tsec_info, num);
283 }
284
281 struct tsec_info_struct tsec_info[2];
282 int num = 0;
283
284#ifdef CONFIG_TSEC1
285 SET_STD_TSEC_INFO(tsec_info[num], 1);
286 if (is_serdes_configured(SGMII_TSEC1)) {
287 puts("eTSEC1 is in sgmii mode.\n");
288 tsec_info[num].flags |= TSEC_SGMII;

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304 return 0;
305 }
306
307 if (is_serdes_configured(SGMII_TSEC1) ||
308 is_serdes_configured(SGMII_TSEC3)) {
309 fsl_sgmii_riser_init(tsec_info, num);
310 }
311
312 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
313 mdio_info.name = DEFAULT_MII_NAME;
314 fsl_pq_mdio_init(bis, &mdio_info);
285
286 tsec_eth_init(bis, tsec_info, num);
287#endif
288 return pci_eth_init(bis);
289}
290
291#if defined(CONFIG_OF_BOARD_SETUP)
292void ft_board_setup(void *blob, bd_t *bd)
293{
294 ft_cpu_setup(blob, bd);
295
296 FT_FSL_PCI_SETUP;
297
298#ifdef CONFIG_FSL_SGMII_RISER
299 fsl_sgmii_riser_fdt_fixup(blob);
300#endif
301}
302#endif
315
316 tsec_eth_init(bis, tsec_info, num);
317#endif
318 return pci_eth_init(bis);
319}
320
321#if defined(CONFIG_OF_BOARD_SETUP)
322void ft_board_setup(void *blob, bd_t *bd)
323{
324 ft_cpu_setup(blob, bd);
325
326 FT_FSL_PCI_SETUP;
327
328#ifdef CONFIG_FSL_SGMII_RISER
329 fsl_sgmii_riser_fdt_fixup(blob);
330#endif
331}
332#endif