mpc8544ds.c (49db23d4529d8f925f1572dbf1226f319f912580) mpc8544ds.c (2f15278c2eb911c668b4fe562130b78cf554d139)
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

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47 return 0;
48}
49
50int checkboard (void)
51{
52 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
53 volatile ccsr_gur_t *gur = &immap->im_gur;
54
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

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47 return 0;
48}
49
50int checkboard (void)
51{
52 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
53 volatile ccsr_gur_t *gur = &immap->im_gur;
54
55 if ((uint)&gur->porpllsr != 0xe00e0000) {
55 if ((uint)&gur->porpllsr != 0xe00e0000) {
56 printf("immap size error %x\n",&gur->porpllsr);
57 }
58 printf ("Board: MPC8544DS\n");
59
60 return 0;
61}
62
63long int

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74 * Initialize and enable DDR ECC.
75 */
76 ddr_enable_ecc(dram_size);
77#endif
78 puts(" DDR: ");
79 return dram_size;
80}
81
56 printf("immap size error %x\n",&gur->porpllsr);
57 }
58 printf ("Board: MPC8544DS\n");
59
60 return 0;
61}
62
63long int

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74 * Initialize and enable DDR ECC.
75 */
76 ddr_enable_ecc(dram_size);
77#endif
78 puts(" DDR: ");
79 return dram_size;
80}
81
82
83#if defined(CFG_DRAM_TEST)
84int
85testdram(void)
86{
87 uint *pstart = (uint *) CFG_MEMTEST_START;
88 uint *pend = (uint *) CFG_MEMTEST_END;
89 uint *p;
90

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114 }
115 }
116
117 printf("DRAM test passed.\n");
118 return 0;
119}
120#endif
121
82#if defined(CFG_DRAM_TEST)
83int
84testdram(void)
85{
86 uint *pstart = (uint *) CFG_MEMTEST_START;
87 uint *pend = (uint *) CFG_MEMTEST_END;
88 uint *p;
89

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113 }
114 }
115
116 printf("DRAM test passed.\n");
117 return 0;
118}
119#endif
120
122
123
124int last_stage_init(void)
125{
126 return 0;
127}
128
129
130unsigned long
131get_board_sys_clk(ulong dummy)

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185
186 return val;
187}
188
189#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
190void
191ft_board_setup(void *blob, bd_t *bd)
192{
121int last_stage_init(void)
122{
123 return 0;
124}
125
126
127unsigned long
128get_board_sys_clk(ulong dummy)

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182
183 return val;
184}
185
186#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
187void
188ft_board_setup(void *blob, bd_t *bd)
189{
193 u32 *p;
194 int len;
190 u32 *p;
191 int len;
195
192
196 ft_cpu_setup(blob, bd);
193 ft_cpu_setup(blob, bd);
197
194
198 p = ft_get_prop(blob, "/memory/reg", &len);
199 if (p != NULL) {
200 *p++ = cpu_to_be32(bd->bi_memstart);
201 *p = cpu_to_be32(bd->bi_memsize);
202 }
195 p = ft_get_prop(blob, "/memory/reg", &len);
196 if (p != NULL) {
197 *p++ = cpu_to_be32(bd->bi_memstart);
198 *p = cpu_to_be32(bd->bi_memsize);
199 }
203}
204#endif
200}
201#endif
205