sdram.c (52c411805c090999f015df8bdf8016fb684746d0) sdram.c (088454cde245b4d431ce0181be8b3cbceea059d6)
1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
8 *

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60
61 /* enable DDR controller */
62 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
63 sync();
64
65 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
66}
67
1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4 *
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
8 *

--- 51 unchanged lines hidden (view full) ---

60
61 /* enable DDR controller */
62 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
63 sync();
64
65 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
66}
67
68phys_size_t initdram(void)
68int initdram(void)
69{
70 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
71 u32 msize;
72
73 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
69{
70 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
71 u32 msize;
72
73 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
74 return -1;
74 return -ENXIO;
75
76 /* DDR SDRAM */
77 msize = fixed_sdram();
78
79 /* return total bus SDRAM size(bytes) -- DDR */
75
76 /* DDR SDRAM */
77 msize = fixed_sdram();
78
79 /* return total bus SDRAM size(bytes) -- DDR */
80 return msize;
80 gd->ram_size = msize;
81
82 return 0;
81}
83}