nand.c (e57ed96baca1222e6cd3d7032691a89d5890bb4a) nand.c (cfa460adfdefcc30d104e1a9ee44994ee349bb7b)
1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this

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35#include <nand.h>
36#include <linux/mtd/mtd.h>
37
38#define SET_CLE 0x10
39#define CLR_CLE ~SET_CLE
40#define SET_ALE 0x08
41#define CLR_ALE ~SET_ALE
42
1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this

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35#include <nand.h>
36#include <linux/mtd/mtd.h>
37
38#define SET_CLE 0x10
39#define CLR_CLE ~SET_CLE
40#define SET_ALE 0x08
41#define CLR_ALE ~SET_ALE
42
43static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
43static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
44{
45 struct nand_chip *this = mtdinfo->priv;
44{
45 struct nand_chip *this = mtdinfo->priv;
46 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
46/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
47 u32 nand_baseaddr = (u32) this->IO_ADDR_W;
48
47 u32 nand_baseaddr = (u32) this->IO_ADDR_W;
48
49 switch (cmd) {
50 case NAND_CTL_SETNCE:
51 case NAND_CTL_CLRNCE:
52 break;
53 case NAND_CTL_SETCLE:
54 nand_baseaddr |= SET_CLE;
55 break;
56 case NAND_CTL_CLRCLE:
57 nand_baseaddr &= CLR_CLE;
58 break;
59 case NAND_CTL_SETALE:
60 nand_baseaddr |= SET_ALE;
61 break;
62 case NAND_CTL_CLRALE:
63 nand_baseaddr |= CLR_ALE;
64 break;
65 case NAND_CTL_SETWP:
66 fbcs->csmr2 |= FBCS_CSMR_WP;
67 break;
68 case NAND_CTL_CLRWP:
69 fbcs->csmr2 &= ~FBCS_CSMR_WP;
70 break;
49 if (ctrl & NAND_CTRL_CHANGE) {
50 if ( ctrl & NAND_CLE )
51 nand_baseaddr |= SET_CLE;
52 else
53 nand_baseaddr &= CLR_CLE;
54 if ( ctrl & NAND_ALE )
55 nand_baseaddr |= SET_ALE;
56 else
57 nand_baseaddr &= CLR_ALE;
71 }
72 this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
58 }
59 this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
60
61 if (cmd != NAND_CMD_NONE)
62 writeb(cmd, this->IO_ADDR_W);
73}
74
75static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
76{
77 struct nand_chip *this = mtdinfo->priv;
78 *((volatile u8 *)(this->IO_ADDR_W)) = byte;
79}
80

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98 /* set up pin configuration */
99 gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
100 gpio->pddr_timer |= 0x08;
101 gpio->ppd_timer |= 0x08;
102 gpio->pclrr_timer = 0;
103 gpio->podr_timer = 0;
104
105 nand->chip_delay = 50;
63}
64
65static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
66{
67 struct nand_chip *this = mtdinfo->priv;
68 *((volatile u8 *)(this->IO_ADDR_W)) = byte;
69}
70

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88 /* set up pin configuration */
89 gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
90 gpio->pddr_timer |= 0x08;
91 gpio->ppd_timer |= 0x08;
92 gpio->pclrr_timer = 0;
93 gpio->podr_timer = 0;
94
95 nand->chip_delay = 50;
106 nand->eccmode = NAND_ECC_SOFT;
107 nand->hwcontrol = nand_hwcontrol;
96 nand->ecc.mode = NAND_ECC_SOFT;
97 nand->cmd_ctrl = nand_hwcontrol;
108 nand->read_byte = nand_read_byte;
109 nand->write_byte = nand_write_byte;
110 nand->dev_ready = nand_dev_ready;
111
112 return 0;
113}
114#endif
98 nand->read_byte = nand_read_byte;
99 nand->write_byte = nand_write_byte;
100 nand->dev_ready = nand_dev_ready;
101
102 return 0;
103}
104#endif