ls1088a.c (e84a324ba7950e88c0df4a2c656f533c723aeaae) ls1088a.c (7769776a603f76ab1b7c1478f6cf8388b3cb5464)
1/*
2 * Copyright 2017 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <i2c.h>
8#include <malloc.h>

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45int checkboard(void)
46{
47 char buf[64];
48 u8 sw;
49 static const char *const freq[] = {"100", "125", "156.25",
50 "100 separate SSCG"};
51 int clock;
52
1/*
2 * Copyright 2017 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <i2c.h>
8#include <malloc.h>

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45int checkboard(void)
46{
47 char buf[64];
48 u8 sw;
49 static const char *const freq[] = {"100", "125", "156.25",
50 "100 separate SSCG"};
51 int clock;
52
53
53#ifdef CONFIG_TARGET_LS1088AQDS
54 printf("Board: LS1088A-QDS, ");
55#else
54 printf("Board: LS1088A-RDB, ");
56 printf("Board: LS1088A-RDB, ");
57#endif
55
56 sw = QIXIS_READ(arch);
57 printf("Board Arch: V%d, ", sw >> 4);
58
58
59 sw = QIXIS_READ(arch);
60 printf("Board Arch: V%d, ", sw >> 4);
61
62#ifdef CONFIG_TARGET_LS1088AQDS
63 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
64#else
59 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
65 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
66#endif
60
67
61
62 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
63
64 sw = QIXIS_READ(brdcfg[0]);
65 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
66
67#ifdef CONFIG_SD_BOOT
68 puts("SD card\n");
69#endif
70 switch (sw) {
68 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
69
70 sw = QIXIS_READ(brdcfg[0]);
71 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
72
73#ifdef CONFIG_SD_BOOT
74 puts("SD card\n");
75#endif
76 switch (sw) {
77#ifdef CONFIG_TARGET_LS1088AQDS
71 case 0:
78 case 0:
72
79 case 1:
80 case 2:
81 case 3:
82 case 4:
83 case 5:
84 case 6:
85 case 7:
86 printf("vBank: %d\n", sw);
87 break;
88 case 8:
89 puts("PromJet\n");
90 break;
91 case 15:
92 puts("IFCCard\n");
93 break;
94 case 14:
95#else
96 case 0:
97#endif
73 puts("QSPI:");
74 sw = QIXIS_READ(brdcfg[0]);
75 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
76 if (sw == 0 || sw == 4)
77 puts("0\n");
78 else if (sw == 1)
79 puts("1\n");
80 else
81 puts("EMU\n");
82 break;
83
84 default:
85 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
86 break;
87 }
88
98 puts("QSPI:");
99 sw = QIXIS_READ(brdcfg[0]);
100 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
101 if (sw == 0 || sw == 4)
102 puts("0\n");
103 else if (sw == 1)
104 puts("1\n");
105 else
106 puts("EMU\n");
107 break;
108
109 default:
110 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
111 break;
112 }
113
89
114#ifdef CONFIG_TARGET_LS1088AQDS
115 printf("FPGA: v%d (%s), build %d",
116 (int)QIXIS_READ(scver), qixis_read_tag(buf),
117 (int)qixis_read_minor());
118 /* the timestamp string contains "\n" at the end */
119 printf(" on %s", qixis_read_time(buf));
120#else
90 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
121 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
122#endif
91
123
92
93 /*
94 * Display the actual SERDES reference clocks as configured by the
95 * dip switches on the board. Note that the SWx registers could
96 * technically be set to force the reference clocks to match the
97 * values that the SERDES expects (or vice versa). For now, however,
98 * we just display both values and hope the user notices when they
99 * don't match.
100 */

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111 clock = (sw >> 0) & 3;
112 printf("Clock2 = %sMHz\n", freq[clock]);
113
114 return 0;
115}
116
117bool if_board_diff_clk(void)
118{
124 /*
125 * Display the actual SERDES reference clocks as configured by the
126 * dip switches on the board. Note that the SWx registers could
127 * technically be set to force the reference clocks to match the
128 * values that the SERDES expects (or vice versa). For now, however,
129 * we just display both values and hope the user notices when they
130 * don't match.
131 */

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142 clock = (sw >> 0) & 3;
143 printf("Clock2 = %sMHz\n", freq[clock]);
144
145 return 0;
146}
147
148bool if_board_diff_clk(void)
149{
150#ifdef CONFIG_TARGET_LS1088AQDS
151 u8 diff_conf = QIXIS_READ(brdcfg[11]);
152 return diff_conf & 0x40;
153#else
119 u8 diff_conf = QIXIS_READ(dutcfg[11]);
120 return diff_conf & 0x80;
154 u8 diff_conf = QIXIS_READ(dutcfg[11]);
155 return diff_conf & 0x80;
156#endif
121}
122
123unsigned long get_board_sys_clk(void)
124{
125 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
126
127 switch (sysclk_conf & 0x0f) {
128 case QIXIS_SYSCLK_83:

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212 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
213
214 /* Select VCO Divider to full rate (000) */
215 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
216 reg &= 0x0f;
217 reg |= 0x70;
218 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
219
157}
158
159unsigned long get_board_sys_clk(void)
160{
161 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
162
163 switch (sysclk_conf & 0x0f) {
164 case QIXIS_SYSCLK_83:

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248 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
249
250 /* Select VCO Divider to full rate (000) */
251 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
252 reg &= 0x0f;
253 reg |= 0x70;
254 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
255
256#ifdef CONFIG_TARGET_LS1088AQDS
257 /* Retimer is connected to I2C1_CH5 */
258 select_i2c_ch_pca9547(I2C_MUX_CH5);
220
259
260 /* Access to Control/Shared register */
261 reg = 0x0;
262 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
263
264 /* Read device revision and ID */
265 i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
266 debug("Retimer version id = 0x%x\n", reg);
267
268 /* Enable Broadcast. All writes target all channel register sets */
269 reg = 0x0c;
270 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
271
272 /* Reset Channel Registers */
273 i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
274 reg |= 0x4;
275 i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
276
277 /* Set data rate as 10.3125 Gbps */
278 reg = 0x90;
279 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
280 reg = 0xb3;
281 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
282 reg = 0x90;
283 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
284 reg = 0xb3;
285 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
286 reg = 0xcd;
287 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
288
289 /* Select VCO Divider to full rate (000) */
290 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
291 reg &= 0x0f;
292 reg |= 0x70;
293 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
294#endif
221 /*return the default channel*/
222 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
223}
224
225int board_init(void)
226{
227 init_final_memctl_regs();
228#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)

--- 104 unchanged lines hidden --- 		295 /*return the default channel*/
296 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
297}
298
299int board_init(void)
300{
301 init_final_memctl_regs();
302#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)

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