ddr.h (e84a324ba7950e88c0df4a2c656f533c723aeaae) ddr.h (7769776a603f76ab1b7c1478f6cf8388b3cb5464)
1/*
2 * Copyright 2017 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1088A_DDR_H__
8#define __LS1088A_DDR_H__

--- 20 unchanged lines hidden (view full) ---

29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
30 */
31#if defined(CONFIG_TARGET_LS1088ARDB)
32
33 {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
34 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
35 {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
36 {}
1/*
2 * Copyright 2017 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1088A_DDR_H__
8#define __LS1088A_DDR_H__

--- 20 unchanged lines hidden (view full) ---

29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
30 */
31#if defined(CONFIG_TARGET_LS1088ARDB)
32
33 {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
34 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
35 {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
36 {}
37#elif defined(CONFIG_TARGET_LS1088AQDS)
38 {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
39 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
40 {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
41 {}
37
38#endif
39};
40
41static const struct board_specific_parameters *udimms[] = {
42 udimm0,
43};
44#endif
42
43#endif
44};
45
46static const struct board_specific_parameters *udimms[] = {
47 udimm0,
48};
49#endif