ls1046ardb.c (a52ff334c5b16e71a58fb75f35394761e645f7e9) ls1046ardb.c (f7244f2c4815aa80a7cd7e9ceaee1969a16acd47)
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>

--- 7 unchanged lines hidden (view full) ---

16#include <ahci.h>
17#include <mmc.h>
18#include <scsi.h>
19#include <fm_eth.h>
20#include <fsl_csu.h>
21#include <fsl_esdhc.h>
22#include <power/mc34vr500_pmic.h>
23#include "cpld.h"
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>

--- 7 unchanged lines hidden (view full) ---

16#include <ahci.h>
17#include <mmc.h>
18#include <scsi.h>
19#include <fm_eth.h>
20#include <fsl_csu.h>
21#include <fsl_esdhc.h>
22#include <power/mc34vr500_pmic.h>
23#include "cpld.h"
24#include <fsl_sec.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27int board_early_init_f(void)
28{
29 fsl_lsch2_early_init_f();
30
31 return 0;

--- 35 unchanged lines hidden (view full) ---

67int board_init(void)
68{
69 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
70
71#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
72 enable_layerscape_ns_access();
73#endif
74
25
26DECLARE_GLOBAL_DATA_PTR;
27
28int board_early_init_f(void)
29{
30 fsl_lsch2_early_init_f();
31
32 return 0;

--- 35 unchanged lines hidden (view full) ---

68int board_init(void)
69{
70 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
71
72#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
73 enable_layerscape_ns_access();
74#endif
75
76#ifdef CONFIG_SECURE_BOOT
77 /*
78 * In case of Secure Boot, the IBR configures the SMMU
79 * to allow only Secure transactions.
80 * SMMU must be reset in bypass mode.
81 * Set the ClientPD bit and Clear the USFCFG Bit
82 */
83 u32 val;
84 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
85 out_le32(SMMU_SCR0, val);
86 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
87 out_le32(SMMU_NSCR0, val);
88#endif
89
90#ifdef CONFIG_FSL_CAAM
91 sec_init();
92#endif
93
75#ifdef CONFIG_FSL_LS_PPA
76 ppa_init();
77#endif
78
79 /* invert AQR105 IRQ pins polarity */
80 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
81
82 return 0;

--- 83 unchanged lines hidden ---
94#ifdef CONFIG_FSL_LS_PPA
95 ppa_init();
96#endif
97
98 /* invert AQR105 IRQ pins polarity */
99 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
100
101 return 0;

--- 83 unchanged lines hidden ---