ls1046aqds.c (2d221489df021393654805536be7effcb9d39702) ls1046aqds.c (4961eafc25d0bfa7ac5f88ec78a7f7501c202fbb)
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/fdt.h>
1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/fdt.h>
14#include <asm/arch/mmu.h>
14#include <asm/arch/soc.h>
15#include <ahci.h>
16#include <hwconfig.h>
17#include <mmc.h>
18#include <scsi.h>
19#include <fm_eth.h>
20#include <fsl_csu.h>
21#include <fsl_esdhc.h>

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144{
145 /*
146 * When resuming from deep sleep, the I2C channel may not be
147 * in the default channel. So, switch to the default channel
148 * before accessing DDR SPD.
149 */
150 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
151 gd->ram_size = initdram(0);
15#include <asm/arch/soc.h>
16#include <ahci.h>
17#include <hwconfig.h>
18#include <mmc.h>
19#include <scsi.h>
20#include <fm_eth.h>
21#include <fsl_csu.h>
22#include <fsl_esdhc.h>

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145{
146 /*
147 * When resuming from deep sleep, the I2C channel may not be
148 * in the default channel. So, switch to the default channel
149 * before accessing DDR SPD.
150 */
151 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
152 gd->ram_size = initdram(0);
153#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
154 /* This will break-before-make MMU for DDR */
155 update_early_mmu_table();
156#endif
152
153 return 0;
154}
155
156int i2c_multiplexer_select_vid_channel(u8 channel)
157{
158 return select_i2c_ch_pca9547(channel);
159}

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158 return 0;
159}
160
161int i2c_multiplexer_select_vid_channel(u8 channel)
162{
163 return select_i2c_ch_pca9547(channel);
164}

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