ls1043aqds.c (cbe7706ab8aab06c18edaa9b120371f9c8012728) ls1043aqds.c (4961eafc25d0bfa7ac5f88ec78a7f7501c202fbb)
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/fdt.h>
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/fdt.h>
14#include <asm/arch/mmu.h>
14#include <asm/arch/soc.h>
15#include <ahci.h>
16#include <hwconfig.h>
17#include <mmc.h>
18#include <scsi.h>
19#include <fm_eth.h>
20#include <fsl_esdhc.h>
21#include <fsl_ifc.h>

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148{
149 /*
150 * When resuming from deep sleep, the I2C channel may not be
151 * in the default channel. So, switch to the default channel
152 * before accessing DDR SPD.
153 */
154 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
155 gd->ram_size = initdram(0);
15#include <asm/arch/soc.h>
16#include <ahci.h>
17#include <hwconfig.h>
18#include <mmc.h>
19#include <scsi.h>
20#include <fm_eth.h>
21#include <fsl_esdhc.h>
22#include <fsl_ifc.h>

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149{
150 /*
151 * When resuming from deep sleep, the I2C channel may not be
152 * in the default channel. So, switch to the default channel
153 * before accessing DDR SPD.
154 */
155 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
156 gd->ram_size = initdram(0);
157#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
158 /* This will break-before-make MMU for DDR */
159 update_early_mmu_table();
160#endif
156
157 return 0;
158}
159
160int i2c_multiplexer_select_vid_channel(u8 channel)
161{
162 return select_i2c_ch_pca9547(channel);
163}

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162 return 0;
163}
164
165int i2c_multiplexer_select_vid_channel(u8 channel)
166{
167 return select_i2c_ch_pca9547(channel);
168}

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