ls1021aqds.c (cbe7706ab8aab06c18edaa9b120371f9c8012728) ls1021aqds.c (02fb2761576be8096ebf1b3f961a2cdb21b422ae)
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>

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17#include <mmc.h>
18#include <fsl_csu.h>
19#include <fsl_esdhc.h>
20#include <fsl_ifc.h>
21#include <fsl_sec.h>
22#include <spl.h>
23#include <fsl_devdis.h>
24#include <fsl_validate.h>
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>

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17#include <mmc.h>
18#include <fsl_csu.h>
19#include <fsl_esdhc.h>
20#include <fsl_ifc.h>
21#include <fsl_sec.h>
22#include <spl.h>
23#include <fsl_devdis.h>
24#include <fsl_validate.h>
25
25#include <fsl_ddr.h>
26#include "../common/sleep.h"
27#include "../common/qixis.h"
28#include "ls1021aqds_qixis.h"
29#ifdef CONFIG_U_QE
30#include <fsl_qe.h>
31#endif
32
33#define PIN_MUX_SEL_CAN 0x03

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428int board_init(void)
429{
430 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
431 unsigned int major;
432
433#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
434 erratum_a010315();
435#endif
26#include "../common/sleep.h"
27#include "../common/qixis.h"
28#include "ls1021aqds_qixis.h"
29#ifdef CONFIG_U_QE
30#include <fsl_qe.h>
31#endif
32
33#define PIN_MUX_SEL_CAN 0x03

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428int board_init(void)
429{
430 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
431 unsigned int major;
432
433#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
434 erratum_a010315();
435#endif
436
436#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
437 erratum_a009942_check_cpo();
438#endif
437 major = get_soc_major_rev();
438 if (major == SOC_MAJOR_VER_1_0) {
439 /* Set CCI-400 control override register to
440 * enable barrier transaction */
441 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
442 }
443
444 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

--- 64 unchanged lines hidden --- 		439 major = get_soc_major_rev();
440 if (major == SOC_MAJOR_VER_1_0) {
441 /* Set CCI-400 control override register to
442 * enable barrier transaction */
443 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
444 }
445
446 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

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