| da850evm.c (ecc98ec18c5b23b399e4aa12d252b719ea4aedb1) | da850evm.c (6652c62e0146411ea2b38fb36336915ffdba99de) |
|---|---|
| 1/* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * --- 321 unchanged lines hidden (view full) --- 330 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 331 return 1; 332 333 return 0; 334} 335 336int board_init(void) 337{ | 1/* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * --- 321 unchanged lines hidden (view full) --- 330 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 331 return 1; 332 333 return 0; 334} 335 336int board_init(void) 337{ |
| 338#ifdef CONFIG_USE_NOR | 338#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) |
| 339 u32 val; 340#endif 341 342#ifndef CONFIG_USE_IRQ 343 irq_init(); 344#endif 345 346#ifdef CONFIG_NAND_DAVINCI --- 34 unchanged lines hidden (view full) --- 381 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 382 383 /* Set the output as low */ 384 val = readl(GPIO_BANK0_REG_SET_ADDR); 385 val |= (0x01 << 11); 386 writel(val, GPIO_BANK0_REG_CLR_ADDR); 387#endif 388 | 339 u32 val; 340#endif 341 342#ifndef CONFIG_USE_IRQ 343 irq_init(); 344#endif 345 346#ifdef CONFIG_NAND_DAVINCI --- 34 unchanged lines hidden (view full) --- 381 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 382 383 /* Set the output as low */ 384 val = readl(GPIO_BANK0_REG_SET_ADDR); 385 val |= (0x01 << 11); 386 writel(val, GPIO_BANK0_REG_CLR_ADDR); 387#endif 388 |
| 389#ifdef CONFIG_DAVINCI_MMC 390 /* Set the GPIO direction as output */ 391 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 392 393 /* Set the output as high */ 394 val = readl(GPIO_BANK0_REG_SET_ADDR); 395 val |= (0x01 << 11); 396 writel(val, GPIO_BANK0_REG_SET_ADDR); 397#endif 398 |
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| 389#ifdef CONFIG_DRIVER_TI_EMAC 390 davinci_emac_mii_mode_sel(HAS_RMII); 391#endif /* CONFIG_DRIVER_TI_EMAC */ 392 393 /* enable the console UART */ 394 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 395 DAVINCI_UART_PWREMU_MGMT_UTRST), 396 &davinci_uart2_ctrl_regs->pwremu_mgmt); --- 108 unchanged lines hidden --- | 399#ifdef CONFIG_DRIVER_TI_EMAC 400 davinci_emac_mii_mode_sel(HAS_RMII); 401#endif /* CONFIG_DRIVER_TI_EMAC */ 402 403 /* enable the console UART */ 404 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 405 DAVINCI_UART_PWREMU_MGMT_UTRST), 406 &davinci_uart2_ctrl_regs->pwremu_mgmt); --- 108 unchanged lines hidden --- |