tables.c (ff94c219e95843fe24710c16a66efdfb6ca536a9) | tables.c (3cf23719b1dc97d17ed649493b0b61641a79ab1f) |
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1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <common.h> 8#include <asm/sfi.h> 9#include <asm/mpspec.h> 10#include <asm/smbios.h> 11#include <asm/tables.h> 12#include <asm/acpi_table.h> | 1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <common.h> 8#include <asm/sfi.h> 9#include <asm/mpspec.h> 10#include <asm/smbios.h> 11#include <asm/tables.h> 12#include <asm/acpi_table.h> |
13#include <asm/coreboot_tables.h> |
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13 14/** 15 * Function prototype to write a specific configuration table 16 * 17 * @addr: start address to write the table 18 * @return: end address of the table 19 */ 20typedef u32 (*table_write)(u32 addr); --- 41 unchanged lines hidden (view full) --- 62 for (i = start; i < n; i++) 63 dest[i] = pad; 64} 65 66void write_tables(void) 67{ 68 u32 rom_table_start = ROM_TABLE_ADDR; 69 u32 rom_table_end; | 14 15/** 16 * Function prototype to write a specific configuration table 17 * 18 * @addr: start address to write the table 19 * @return: end address of the table 20 */ 21typedef u32 (*table_write)(u32 addr); --- 41 unchanged lines hidden (view full) --- 63 for (i = start; i < n; i++) 64 dest[i] = pad; 65} 66 67void write_tables(void) 68{ 69 u32 rom_table_start = ROM_TABLE_ADDR; 70 u32 rom_table_end; |
71#ifdef CONFIG_SEABIOS |
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70 u32 high_table, table_size; | 72 u32 high_table, table_size; |
73 struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1]; 74#endif |
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71 int i; 72 73 for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) { 74 rom_table_end = table_write_funcs[i](rom_table_start); 75 rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN); 76 | 75 int i; 76 77 for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) { 78 rom_table_end = table_write_funcs[i](rom_table_start); 79 rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN); 80 |
81#ifdef CONFIG_SEABIOS |
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77 table_size = rom_table_end - rom_table_start; 78 high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size); 79 if (high_table) { 80 memset((void *)high_table, 0, table_size); 81 table_write_funcs[i](high_table); | 82 table_size = rom_table_end - rom_table_start; 83 high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size); 84 if (high_table) { 85 memset((void *)high_table, 0, table_size); 86 table_write_funcs[i](high_table); |
87 88 cfg_tables[i].start = high_table; 89 cfg_tables[i].size = table_size; |
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82 } else { 83 printf("%d: no memory for configuration tables\n", i); 84 } | 90 } else { 91 printf("%d: no memory for configuration tables\n", i); 92 } |
93#endif |
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85 86 rom_table_start = rom_table_end; 87 } | 94 95 rom_table_start = rom_table_end; 96 } |
97 98#ifdef CONFIG_SEABIOS 99 /* make sure the last item is zero */ 100 cfg_tables[i].size = 0; 101 write_coreboot_table(CB_TABLE_ADDR, cfg_tables); 102#endif |
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88} | 103} |