minnowmax.dts (80af39842e64a44258ab5eb913659e29fc319903) minnowmax.dts (f2b85ab5e6a91e29c1d64304be371753d75ed172)
1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8

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145 compatible = "intel,pci-baytrail", "pci-x86";
146 #address-cells = <3>;
147 #size-cells = <2>;
148 u-boot,dm-pre-reloc;
149 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
150 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
151 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
152
1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8

--- 136 unchanged lines hidden (view full) ---

145 compatible = "intel,pci-baytrail", "pci-x86";
146 #address-cells = <3>;
147 #size-cells = <2>;
148 u-boot,dm-pre-reloc;
149 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
150 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
151 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
152
153 irq-router@1f,0 {
153 pch@1f,0 {
154 reg = <0x0000f800 0 0 0 0>;
154 reg = <0x0000f800 0 0 0 0>;
155 compatible = "intel,irq-router";
156 intel,pirq-config = "ibase";
157 intel,ibase-offset = <0x50>;
158 intel,pirq-link = <8 8>;
159 intel,pirq-mask = <0xdee0>;
160 intel,pirq-routing = <
161 /* BayTrail PCI devices */
162 PCI_BDF(0, 2, 0) INTA PIRQA
163 PCI_BDF(0, 3, 0) INTA PIRQA
164 PCI_BDF(0, 16, 0) INTA PIRQA
165 PCI_BDF(0, 17, 0) INTA PIRQA
166 PCI_BDF(0, 18, 0) INTA PIRQA
167 PCI_BDF(0, 19, 0) INTA PIRQA
168 PCI_BDF(0, 20, 0) INTA PIRQA
169 PCI_BDF(0, 21, 0) INTA PIRQA
170 PCI_BDF(0, 22, 0) INTA PIRQA
171 PCI_BDF(0, 23, 0) INTA PIRQA
172 PCI_BDF(0, 24, 0) INTA PIRQA
173 PCI_BDF(0, 24, 1) INTC PIRQC
174 PCI_BDF(0, 24, 2) INTD PIRQD
175 PCI_BDF(0, 24, 3) INTB PIRQB
176 PCI_BDF(0, 24, 4) INTA PIRQA
177 PCI_BDF(0, 24, 5) INTC PIRQC
178 PCI_BDF(0, 24, 6) INTD PIRQD
179 PCI_BDF(0, 24, 7) INTB PIRQB
180 PCI_BDF(0, 26, 0) INTA PIRQA
181 PCI_BDF(0, 27, 0) INTA PIRQA
182 PCI_BDF(0, 28, 0) INTA PIRQA
183 PCI_BDF(0, 28, 1) INTB PIRQB
184 PCI_BDF(0, 28, 2) INTC PIRQC
185 PCI_BDF(0, 28, 3) INTD PIRQD
186 PCI_BDF(0, 29, 0) INTA PIRQA
187 PCI_BDF(0, 30, 0) INTA PIRQA
188 PCI_BDF(0, 30, 1) INTD PIRQD
189 PCI_BDF(0, 30, 2) INTB PIRQB
190 PCI_BDF(0, 30, 3) INTC PIRQC
191 PCI_BDF(0, 30, 4) INTD PIRQD
192 PCI_BDF(0, 30, 5) INTB PIRQB
193 PCI_BDF(0, 31, 3) INTB PIRQB
155 compatible = "pci8086,0f1c", "intel,pch9";
194
156
195 /* PCIe root ports downstream interrupts */
196 PCI_BDF(1, 0, 0) INTA PIRQA
197 PCI_BDF(1, 0, 0) INTB PIRQB
198 PCI_BDF(1, 0, 0) INTC PIRQC
199 PCI_BDF(1, 0, 0) INTD PIRQD
200 PCI_BDF(2, 0, 0) INTA PIRQB
201 PCI_BDF(2, 0, 0) INTB PIRQC
202 PCI_BDF(2, 0, 0) INTC PIRQD
203 PCI_BDF(2, 0, 0) INTD PIRQA
204 PCI_BDF(3, 0, 0) INTA PIRQC
205 PCI_BDF(3, 0, 0) INTB PIRQD
206 PCI_BDF(3, 0, 0) INTC PIRQA
207 PCI_BDF(3, 0, 0) INTD PIRQB
208 PCI_BDF(4, 0, 0) INTA PIRQD
209 PCI_BDF(4, 0, 0) INTB PIRQA
210 PCI_BDF(4, 0, 0) INTC PIRQB
211 PCI_BDF(4, 0, 0) INTD PIRQC
212 >;
157 irq-router {
158 compatible = "intel,irq-router";
159 intel,pirq-config = "ibase";
160 intel,ibase-offset = <0x50>;
161 intel,pirq-link = <8 8>;
162 intel,pirq-mask = <0xdee0>;
163 intel,pirq-routing = <
164 /* BayTrail PCI devices */
165 PCI_BDF(0, 2, 0) INTA PIRQA
166 PCI_BDF(0, 3, 0) INTA PIRQA
167 PCI_BDF(0, 16, 0) INTA PIRQA
168 PCI_BDF(0, 17, 0) INTA PIRQA
169 PCI_BDF(0, 18, 0) INTA PIRQA
170 PCI_BDF(0, 19, 0) INTA PIRQA
171 PCI_BDF(0, 20, 0) INTA PIRQA
172 PCI_BDF(0, 21, 0) INTA PIRQA
173 PCI_BDF(0, 22, 0) INTA PIRQA
174 PCI_BDF(0, 23, 0) INTA PIRQA
175 PCI_BDF(0, 24, 0) INTA PIRQA
176 PCI_BDF(0, 24, 1) INTC PIRQC
177 PCI_BDF(0, 24, 2) INTD PIRQD
178 PCI_BDF(0, 24, 3) INTB PIRQB
179 PCI_BDF(0, 24, 4) INTA PIRQA
180 PCI_BDF(0, 24, 5) INTC PIRQC
181 PCI_BDF(0, 24, 6) INTD PIRQD
182 PCI_BDF(0, 24, 7) INTB PIRQB
183 PCI_BDF(0, 26, 0) INTA PIRQA
184 PCI_BDF(0, 27, 0) INTA PIRQA
185 PCI_BDF(0, 28, 0) INTA PIRQA
186 PCI_BDF(0, 28, 1) INTB PIRQB
187 PCI_BDF(0, 28, 2) INTC PIRQC
188 PCI_BDF(0, 28, 3) INTD PIRQD
189 PCI_BDF(0, 29, 0) INTA PIRQA
190 PCI_BDF(0, 30, 0) INTA PIRQA
191 PCI_BDF(0, 30, 1) INTD PIRQD
192 PCI_BDF(0, 30, 2) INTB PIRQB
193 PCI_BDF(0, 30, 3) INTC PIRQC
194 PCI_BDF(0, 30, 4) INTD PIRQD
195 PCI_BDF(0, 30, 5) INTB PIRQB
196 PCI_BDF(0, 31, 3) INTB PIRQB
197
198 /*
199 * PCIe root ports downstream
200 * interrupts
201 */
202 PCI_BDF(1, 0, 0) INTA PIRQA
203 PCI_BDF(1, 0, 0) INTB PIRQB
204 PCI_BDF(1, 0, 0) INTC PIRQC
205 PCI_BDF(1, 0, 0) INTD PIRQD
206 PCI_BDF(2, 0, 0) INTA PIRQB
207 PCI_BDF(2, 0, 0) INTB PIRQC
208 PCI_BDF(2, 0, 0) INTC PIRQD
209 PCI_BDF(2, 0, 0) INTD PIRQA
210 PCI_BDF(3, 0, 0) INTA PIRQC
211 PCI_BDF(3, 0, 0) INTB PIRQD
212 PCI_BDF(3, 0, 0) INTC PIRQA
213 PCI_BDF(3, 0, 0) INTD PIRQB
214 PCI_BDF(4, 0, 0) INTA PIRQD
215 PCI_BDF(4, 0, 0) INTB PIRQA
216 PCI_BDF(4, 0, 0) INTC PIRQB
217 PCI_BDF(4, 0, 0) INTD PIRQC
218 >;
219 };
220
221 spi {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "intel,ich-spi";
225 spi-flash@0 {
226 #address-cells = <1>;
227 #size-cells = <1>;
228 reg = <0>;
229 compatible = "stmicro,n25q064a",
230 "spi-flash";
231 memory-map = <0xff800000 0x00800000>;
232 rw-mrc-cache {
233 label = "rw-mrc-cache";
234 reg = <0x006f0000 0x00010000>;
235 };
236 };
237 };
213 };
214 };
215
216 fsp {
217 compatible = "intel,baytrail-fsp";
218 fsp,mrc-init-tseg-size = <0>;
219 fsp,mrc-init-mmio-size = <0x800>;
220 fsp,mrc-init-spd-addr1 = <0xa0>;

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264 fsp,dimm-twr = <0xc>;
265 fsp,dimm-twtr = <6>;
266 fsp,dimm-trrd = <6>;
267 fsp,dimm-trtp = <6>;
268 fsp,dimm-tfaw = <0x14>;
269 };
270 };
271
238 };
239 };
240
241 fsp {
242 compatible = "intel,baytrail-fsp";
243 fsp,mrc-init-tseg-size = <0>;
244 fsp,mrc-init-mmio-size = <0x800>;
245 fsp,mrc-init-spd-addr1 = <0xa0>;

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289 fsp,dimm-twr = <0xc>;
290 fsp,dimm-twtr = <6>;
291 fsp,dimm-trrd = <6>;
292 fsp,dimm-trtp = <6>;
293 fsp,dimm-tfaw = <0x14>;
294 };
295 };
296
272 spi {
273 #address-cells = <1>;
274 #size-cells = <0>;
275 compatible = "intel,ich-spi";
276 spi-flash@0 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 reg = <0>;
280 compatible = "stmicro,n25q064a", "spi-flash";
281 memory-map = <0xff800000 0x00800000>;
282 rw-mrc-cache {
283 label = "rw-mrc-cache";
284 reg = <0x006f0000 0x00010000>;
285 };
286 };
287 };
288
289 microcode {
290 update@0 {
291#include "microcode/m0130673322.dtsi"
292 };
293 update@1 {
294#include "microcode/m0130679901.dtsi"
295 };
296 };
297
298};
297 microcode {
298 update@0 {
299#include "microcode/m0130673322.dtsi"
300 };
301 update@1 {
302#include "microcode/m0130679901.dtsi"
303 };
304 };
305
306};