crownbay.dts (c5c5c201fe37a02e9edf99b0a2ba9353d9d55ddf) crownbay.dts (f2b85ab5e6a91e29c1d64304be371753d75ed172)
1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8

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67 * PCH as the console, change this property to &pciuart#.
68 *
69 * For example, stdout-path = &pciuart0 will use the first
70 * UART on Topcliff PCH.
71 */
72 stdout-path = "/serial";
73 };
74
1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8

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67 * PCH as the console, change this property to &pciuart#.
68 *
69 * For example, stdout-path = &pciuart0 will use the first
70 * UART on Topcliff PCH.
71 */
72 stdout-path = "/serial";
73 };
74
75 spi {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 compatible = "intel,ich-spi";
79 spi-flash@0 {
80 reg = <0>;
81 compatible = "sst,25vf016b", "spi-flash";
82 memory-map = <0xffe00000 0x00200000>;
83 };
84 };
85
86 microcode {
87 update@0 {
88#include "microcode/m0220661105_cv.dtsi"
89 };
90 };
91
92 pci {
93 #address-cells = <3>;

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165 0x01025410 0x0 0x0 0x0 0x0>;
166 reg-shift = <0>;
167 clock-frequency = <1843200>;
168 current-speed = <115200>;
169 };
170 };
171 };
172
75 microcode {
76 update@0 {
77#include "microcode/m0220661105_cv.dtsi"
78 };
79 };
80
81 pci {
82 #address-cells = <3>;

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154 0x01025410 0x0 0x0 0x0 0x0>;
155 reg-shift = <0>;
156 clock-frequency = <1843200>;
157 current-speed = <115200>;
158 };
159 };
160 };
161
173 irq-router@1f,0 {
162 pch@1f,0 {
174 reg = <0x0000f800 0 0 0 0>;
163 reg = <0x0000f800 0 0 0 0>;
175 compatible = "intel,irq-router";
176 intel,pirq-config = "pci";
177 intel,pirq-link = <0x60 8>;
178 intel,pirq-mask = <0xcee0>;
179 intel,pirq-routing = <
180 /* TunnelCreek PCI devices */
181 PCI_BDF(0, 2, 0) INTA PIRQE
182 PCI_BDF(0, 3, 0) INTA PIRQF
183 PCI_BDF(0, 23, 0) INTA PIRQA
184 PCI_BDF(0, 23, 0) INTB PIRQB
185 PCI_BDF(0, 23, 0) INTC PIRQC
186 PCI_BDF(0, 23, 0) INTD PIRQD
187 PCI_BDF(0, 24, 0) INTA PIRQB
188 PCI_BDF(0, 24, 0) INTB PIRQC
189 PCI_BDF(0, 24, 0) INTC PIRQD
190 PCI_BDF(0, 24, 0) INTD PIRQA
191 PCI_BDF(0, 25, 0) INTA PIRQC
192 PCI_BDF(0, 25, 0) INTB PIRQD
193 PCI_BDF(0, 25, 0) INTC PIRQA
194 PCI_BDF(0, 25, 0) INTD PIRQB
195 PCI_BDF(0, 26, 0) INTA PIRQD
196 PCI_BDF(0, 26, 0) INTB PIRQA
197 PCI_BDF(0, 26, 0) INTC PIRQB
198 PCI_BDF(0, 26, 0) INTD PIRQC
199 PCI_BDF(0, 27, 0) INTA PIRQG
200 /*
201 * Topcliff PCI devices
202 *
203 * Note on the Crown Bay board, Topcliff chipset
204 * is connected to TunnelCreek PCIe port 0, so
205 * its bus number is 1 for its PCIe port and 2
206 * for its PCI devices per U-Boot current PCI
207 * bus enumeration algorithm.
208 */
209 PCI_BDF(1, 0, 0) INTA PIRQA
210 PCI_BDF(2, 0, 1) INTA PIRQA
211 PCI_BDF(2, 0, 2) INTA PIRQA
212 PCI_BDF(2, 2, 0) INTB PIRQD
213 PCI_BDF(2, 2, 1) INTB PIRQD
214 PCI_BDF(2, 2, 2) INTB PIRQD
215 PCI_BDF(2, 2, 3) INTB PIRQD
216 PCI_BDF(2, 2, 4) INTB PIRQD
217 PCI_BDF(2, 4, 0) INTC PIRQC
218 PCI_BDF(2, 4, 1) INTC PIRQC
219 PCI_BDF(2, 6, 0) INTD PIRQB
220 PCI_BDF(2, 8, 0) INTA PIRQA
221 PCI_BDF(2, 8, 1) INTA PIRQA
222 PCI_BDF(2, 8, 2) INTA PIRQA
223 PCI_BDF(2, 8, 3) INTA PIRQA
224 PCI_BDF(2, 10, 0) INTB PIRQD
225 PCI_BDF(2, 10, 1) INTB PIRQD
226 PCI_BDF(2, 10, 2) INTB PIRQD
227 PCI_BDF(2, 10, 3) INTB PIRQD
228 PCI_BDF(2, 10, 4) INTB PIRQD
229 PCI_BDF(2, 12, 0) INTC PIRQC
230 PCI_BDF(2, 12, 1) INTC PIRQC
231 PCI_BDF(2, 12, 2) INTC PIRQC
232 PCI_BDF(2, 12, 3) INTC PIRQC
233 PCI_BDF(2, 12, 4) INTC PIRQC
234 >;
164 compatible = "intel,pch7";
165
166 irq-router {
167 compatible = "intel,irq-router";
168 intel,pirq-config = "pci";
169 intel,pirq-link = <0x60 8>;
170 intel,pirq-mask = <0xcee0>;
171 intel,pirq-routing = <
172 /* TunnelCreek PCI devices */
173 PCI_BDF(0, 2, 0) INTA PIRQE
174 PCI_BDF(0, 3, 0) INTA PIRQF
175 PCI_BDF(0, 23, 0) INTA PIRQA
176 PCI_BDF(0, 23, 0) INTB PIRQB
177 PCI_BDF(0, 23, 0) INTC PIRQC
178 PCI_BDF(0, 23, 0) INTD PIRQD
179 PCI_BDF(0, 24, 0) INTA PIRQB
180 PCI_BDF(0, 24, 0) INTB PIRQC
181 PCI_BDF(0, 24, 0) INTC PIRQD
182 PCI_BDF(0, 24, 0) INTD PIRQA
183 PCI_BDF(0, 25, 0) INTA PIRQC
184 PCI_BDF(0, 25, 0) INTB PIRQD
185 PCI_BDF(0, 25, 0) INTC PIRQA
186 PCI_BDF(0, 25, 0) INTD PIRQB
187 PCI_BDF(0, 26, 0) INTA PIRQD
188 PCI_BDF(0, 26, 0) INTB PIRQA
189 PCI_BDF(0, 26, 0) INTC PIRQB
190 PCI_BDF(0, 26, 0) INTD PIRQC
191 PCI_BDF(0, 27, 0) INTA PIRQG
192 /*
193 * Topcliff PCI devices
194 *
195 * Note on the Crown Bay board, Topcliff
196 * chipset is connected to TunnelCreek
197 * PCIe port 0, so its bus number is 1
198 * for its PCIe port and 2 for its PCI
199 * devices per U-Boot current PCI bus
200 * enumeration algorithm.
201 */
202 PCI_BDF(1, 0, 0) INTA PIRQA
203 PCI_BDF(2, 0, 1) INTA PIRQA
204 PCI_BDF(2, 0, 2) INTA PIRQA
205 PCI_BDF(2, 2, 0) INTB PIRQD
206 PCI_BDF(2, 2, 1) INTB PIRQD
207 PCI_BDF(2, 2, 2) INTB PIRQD
208 PCI_BDF(2, 2, 3) INTB PIRQD
209 PCI_BDF(2, 2, 4) INTB PIRQD
210 PCI_BDF(2, 4, 0) INTC PIRQC
211 PCI_BDF(2, 4, 1) INTC PIRQC
212 PCI_BDF(2, 6, 0) INTD PIRQB
213 PCI_BDF(2, 8, 0) INTA PIRQA
214 PCI_BDF(2, 8, 1) INTA PIRQA
215 PCI_BDF(2, 8, 2) INTA PIRQA
216 PCI_BDF(2, 8, 3) INTA PIRQA
217 PCI_BDF(2, 10, 0) INTB PIRQD
218 PCI_BDF(2, 10, 1) INTB PIRQD
219 PCI_BDF(2, 10, 2) INTB PIRQD
220 PCI_BDF(2, 10, 3) INTB PIRQD
221 PCI_BDF(2, 10, 4) INTB PIRQD
222 PCI_BDF(2, 12, 0) INTC PIRQC
223 PCI_BDF(2, 12, 1) INTC PIRQC
224 PCI_BDF(2, 12, 2) INTC PIRQC
225 PCI_BDF(2, 12, 3) INTC PIRQC
226 PCI_BDF(2, 12, 4) INTC PIRQC
227 >;
228 };
229
230 spi {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "intel,ich-spi";
234 spi-flash@0 {
235 reg = <0>;
236 compatible = "sst,25vf016b",
237 "spi-flash";
238 memory-map = <0xffe00000 0x00200000>;
239 };
240 };
235 };
236 };
237
238};
241 };
242 };
243
244};