sun5i.dtsi (c6b968da78ce3fa7224c0ddf15fe170c7c05b27e) sun5i.dtsi (13b36face7adebd790c0b201792ec47b77d2fb0c)
1/*
2 * Copyright 2012-2015 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a

--- 30 unchanged lines hidden (view full) ---

39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "skeleton.dtsi"
46
1/*
2 * Copyright 2012-2015 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a

--- 30 unchanged lines hidden (view full) ---

39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "skeleton.dtsi"
46
47#include <dt-bindings/clock/sun4i-a10-pll2.h>
47#include <dt-bindings/clock/sun5i-ccu.h>
48#include <dt-bindings/dma/sun4i-a10.h>
48#include <dt-bindings/dma/sun4i-a10.h>
49#include <dt-bindings/pinctrl/sun4i-a10.h>
49#include <dt-bindings/reset/sun5i-ccu.h>
50
51/ {
52 interrupt-parent = <&intc>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a8";
61 reg = <0x0>;
50
51/ {
52 interrupt-parent = <&intc>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a8";
61 reg = <0x0>;
62 clocks = <&cpu>;
62 clocks = <&ccu CLK_CPU>;
63 };
64 };
65
63 };
64 };
65
66 clocks {
66 chosen {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
71 /*
72 * This is a dummy clock, to be used as placeholder on
73 * other mux clocks when a specific parent clock is not
74 * yet implemented. It should be dropped when the driver
75 * is complete.
76 */
77 dummy: dummy {
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
71 framebuffer@0 {
72 compatible = "allwinner,simple-framebuffer",
73 "simple-framebuffer";
74 allwinner,pipeline = "de_be0-lcd0";
75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
77 status = "disabled";
81 };
82
78 };
79
83 osc24M: clk@01c20050 {
80 framebuffer@1 {
81 compatible = "allwinner,simple-framebuffer",
82 "simple-framebuffer";
83 allwinner,pipeline = "de_be0-lcd0-tve0";
84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
87 status = "disabled";
88 };
89 };
90
91 clocks {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 osc24M: clk@1c20050 {
84 #clock-cells = <0>;
97 #clock-cells = <0>;
85 compatible = "allwinner,sun4i-a10-osc-clk";
86 reg = <0x01c20050 0x4>;
98 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 clock-output-names = "osc24M";
89 };
90
99 clock-frequency = <24000000>;
100 clock-output-names = "osc24M";
101 };
102
91 osc3M: osc3M_clk {
92 compatible = "fixed-factor-clock";
93 #clock-cells = <0>;
94 clock-div = <8>;
95 clock-mult = <1>;
96 clocks = <&osc24M>;
97 clock-output-names = "osc3M";
98 };
99
100 osc32k: clk@0 {
101 #clock-cells = <0>;
102 compatible = "fixed-clock";
103 clock-frequency = <32768>;
104 clock-output-names = "osc32k";
105 };
103 osc32k: clk@0 {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-frequency = <32768>;
107 clock-output-names = "osc32k";
108 };
106
107 pll1: clk@01c20000 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun4i-a10-pll1-clk";
110 reg = <0x01c20000 0x4>;
111 clocks = <&osc24M>;
112 clock-output-names = "pll1";
113 };
114
115 pll2: clk@01c20008 {
116 #clock-cells = <1>;
117 compatible = "allwinner,sun5i-a13-pll2-clk";
118 reg = <0x01c20008 0x8>;
119 clocks = <&osc24M>;
120 clock-output-names = "pll2-1x", "pll2-2x",
121 "pll2-4x", "pll2-8x";
122 };
123
124 pll3: clk@01c20010 {
125 #clock-cells = <0>;
126 compatible = "allwinner,sun4i-a10-pll3-clk";
127 reg = <0x01c20010 0x4>;
128 clocks = <&osc3M>;
129 clock-output-names = "pll3";
130 };
131
132 pll3x2: pll3x2_clk {
133 compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
134 #clock-cells = <0>;
135 clock-div = <1>;
136 clock-mult = <2>;
137 clocks = <&pll3>;
138 clock-output-names = "pll3-2x";
139 };
140
141 pll4: clk@01c20018 {
142 #clock-cells = <0>;
143 compatible = "allwinner,sun4i-a10-pll1-clk";
144 reg = <0x01c20018 0x4>;
145 clocks = <&osc24M>;
146 clock-output-names = "pll4";
147 };
148
149 pll5: clk@01c20020 {
150 #clock-cells = <1>;
151 compatible = "allwinner,sun4i-a10-pll5-clk";
152 reg = <0x01c20020 0x4>;
153 clocks = <&osc24M>;
154 clock-output-names = "pll5_ddr", "pll5_other";
155 };
156
157 pll6: clk@01c20028 {
158 #clock-cells = <1>;
159 compatible = "allwinner,sun4i-a10-pll6-clk";
160 reg = <0x01c20028 0x4>;
161 clocks = <&osc24M>;
162 clock-output-names = "pll6_sata", "pll6_other", "pll6";
163 };
164
165 pll7: clk@01c20030 {
166 #clock-cells = <0>;
167 compatible = "allwinner,sun4i-a10-pll3-clk";
168 reg = <0x01c20030 0x4>;
169 clocks = <&osc3M>;
170 clock-output-names = "pll7";
171 };
172
173 pll7x2: pll7x2_clk {
174 compatible = "fixed-factor-clock";
175 #clock-cells = <0>;
176 clock-div = <1>;
177 clock-mult = <2>;
178 clocks = <&pll7>;
179 clock-output-names = "pll7-2x";
180 };
181
182 /* dummy is 200M */
183 cpu: cpu@01c20054 {
184 #clock-cells = <0>;
185 compatible = "allwinner,sun4i-a10-cpu-clk";
186 reg = <0x01c20054 0x4>;
187 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
188 clock-output-names = "cpu";
189 };
190
191 axi: axi@01c20054 {
192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-a10-axi-clk";
194 reg = <0x01c20054 0x4>;
195 clocks = <&cpu>;
196 clock-output-names = "axi";
197 };
198
199 ahb: ahb@01c20054 {
200 #clock-cells = <0>;
201 compatible = "allwinner,sun5i-a13-ahb-clk";
202 reg = <0x01c20054 0x4>;
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
204 clock-output-names = "ahb";
205 /*
206 * Use PLL6 as parent, instead of CPU/AXI
207 * which has rate changes due to cpufreq
208 */
209 assigned-clocks = <&ahb>;
210 assigned-clock-parents = <&pll6 1>;
211 };
212
213 apb0: apb0@01c20054 {
214 #clock-cells = <0>;
215 compatible = "allwinner,sun4i-a10-apb0-clk";
216 reg = <0x01c20054 0x4>;
217 clocks = <&ahb>;
218 clock-output-names = "apb0";
219 };
220
221 apb1: clk@01c20058 {
222 #clock-cells = <0>;
223 compatible = "allwinner,sun4i-a10-apb1-clk";
224 reg = <0x01c20058 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
226 clock-output-names = "apb1";
227 };
228
229 axi_gates: clk@01c2005c {
230 #clock-cells = <1>;
231 compatible = "allwinner,sun4i-a10-axi-gates-clk";
232 reg = <0x01c2005c 0x4>;
233 clocks = <&axi>;
234 clock-indices = <0>;
235 clock-output-names = "axi_dram";
236 };
237
238 nand_clk: clk@01c20080 {
239 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c20080 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "nand";
244 };
245
246 ms_clk: clk@01c20084 {
247 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c20084 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "ms";
252 };
253
254 mmc0_clk: clk@01c20088 {
255 #clock-cells = <1>;
256 compatible = "allwinner,sun4i-a10-mmc-clk";
257 reg = <0x01c20088 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "mmc0",
260 "mmc0_output",
261 "mmc0_sample";
262 };
263
264 mmc1_clk: clk@01c2008c {
265 #clock-cells = <1>;
266 compatible = "allwinner,sun4i-a10-mmc-clk";
267 reg = <0x01c2008c 0x4>;
268 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
269 clock-output-names = "mmc1",
270 "mmc1_output",
271 "mmc1_sample";
272 };
273
274 mmc2_clk: clk@01c20090 {
275 #clock-cells = <1>;
276 compatible = "allwinner,sun4i-a10-mmc-clk";
277 reg = <0x01c20090 0x4>;
278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
279 clock-output-names = "mmc2",
280 "mmc2_output",
281 "mmc2_sample";
282 };
283
284 ts_clk: clk@01c20098 {
285 #clock-cells = <0>;
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c20098 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "ts";
290 };
291
292 ss_clk: clk@01c2009c {
293 #clock-cells = <0>;
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c2009c 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "ss";
298 };
299
300 spi0_clk: clk@01c200a0 {
301 #clock-cells = <0>;
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c200a0 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "spi0";
306 };
307
308 spi1_clk: clk@01c200a4 {
309 #clock-cells = <0>;
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c200a4 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "spi1";
314 };
315
316 spi2_clk: clk@01c200a8 {
317 #clock-cells = <0>;
318 compatible = "allwinner,sun4i-a10-mod0-clk";
319 reg = <0x01c200a8 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "spi2";
322 };
323
324 ir0_clk: clk@01c200b0 {
325 #clock-cells = <0>;
326 compatible = "allwinner,sun4i-a10-mod0-clk";
327 reg = <0x01c200b0 0x4>;
328 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
329 clock-output-names = "ir0";
330 };
331
332 usb_clk: clk@01c200cc {
333 #clock-cells = <1>;
334 #reset-cells = <1>;
335 compatible = "allwinner,sun5i-a13-usb-clk";
336 reg = <0x01c200cc 0x4>;
337 clocks = <&pll6 1>;
338 clock-output-names = "usb_ohci0", "usb_phy";
339 };
340
341 codec_clk: clk@01c20140 {
342 #clock-cells = <0>;
343 compatible = "allwinner,sun4i-a10-codec-clk";
344 reg = <0x01c20140 0x4>;
345 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
346 clock-output-names = "codec";
347 };
348
349 mbus_clk: clk@01c2015c {
350 #clock-cells = <0>;
351 compatible = "allwinner,sun5i-a13-mbus-clk";
352 reg = <0x01c2015c 0x4>;
353 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
354 clock-output-names = "mbus";
355 };
356 };
357
109 };
110
358 soc@01c00000 {
111 soc@1c00000 {
359 compatible = "simple-bus";
360 #address-cells = <1>;
361 #size-cells = <1>;
362 ranges;
363
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 ranges;
116
364 sram-controller@01c00000 {
117 sram-controller@1c00000 {
365 compatible = "allwinner,sun4i-a10-sram-controller";
366 reg = <0x01c00000 0x30>;
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges;
370
118 compatible = "allwinner,sun4i-a10-sram-controller";
119 reg = <0x01c00000 0x30>;
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges;
123
371 sram_a: sram@00000000 {
124 sram_a: sram@0 {
372 compatible = "mmio-sram";
373 reg = <0x00000000 0xc000>;
374 #address-cells = <1>;
375 #size-cells = <1>;
376 ranges = <0 0x00000000 0xc000>;
377 };
378
125 compatible = "mmio-sram";
126 reg = <0x00000000 0xc000>;
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0 0x00000000 0xc000>;
130 };
131
379 sram_d: sram@00010000 {
132 emac_sram: sram-section@8000 {
133 compatible = "allwinner,sun4i-a10-sram-a3-a4";
134 reg = <0x8000 0x4000>;
135 status = "disabled";
136 };
137
138 sram_d: sram@10000 {
380 compatible = "mmio-sram";
381 reg = <0x00010000 0x1000>;
382 #address-cells = <1>;
383 #size-cells = <1>;
384 ranges = <0 0x00010000 0x1000>;
385
139 compatible = "mmio-sram";
140 reg = <0x00010000 0x1000>;
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges = <0 0x00010000 0x1000>;
144
386 otg_sram: sram-section@0000 {
145 otg_sram: sram-section@0 {
387 compatible = "allwinner,sun4i-a10-sram-d";
388 reg = <0x0000 0x1000>;
389 status = "disabled";
390 };
391 };
392 };
393
146 compatible = "allwinner,sun4i-a10-sram-d";
147 reg = <0x0000 0x1000>;
148 status = "disabled";
149 };
150 };
151 };
152
394 dma: dma-controller@01c02000 {
153 dma: dma-controller@1c02000 {
395 compatible = "allwinner,sun4i-a10-dma";
396 reg = <0x01c02000 0x1000>;
397 interrupts = <27>;
154 compatible = "allwinner,sun4i-a10-dma";
155 reg = <0x01c02000 0x1000>;
156 interrupts = <27>;
398 clocks = <&ahb_gates 6>;
157 clocks = <&ccu CLK_AHB_DMA>;
399 #dma-cells = <2>;
400 };
401
158 #dma-cells = <2>;
159 };
160
402 spi0: spi@01c05000 {
161 nfc: nand@1c03000 {
162 compatible = "allwinner,sun4i-a10-nand";
163 reg = <0x01c03000 0x1000>;
164 interrupts = <37>;
165 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
166 clock-names = "ahb", "mod";
167 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
168 dma-names = "rxtx";
169 status = "disabled";
170 #address-cells = <1>;
171 #size-cells = <0>;
172 };
173
174 spi0: spi@1c05000 {
403 compatible = "allwinner,sun4i-a10-spi";
404 reg = <0x01c05000 0x1000>;
405 interrupts = <10>;
175 compatible = "allwinner,sun4i-a10-spi";
176 reg = <0x01c05000 0x1000>;
177 interrupts = <10>;
406 clocks = <&ahb_gates 20>, <&spi0_clk>;
178 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
407 clock-names = "ahb", "mod";
408 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
409 <&dma SUN4I_DMA_DEDICATED 26>;
410 dma-names = "rx", "tx";
411 status = "disabled";
412 #address-cells = <1>;
413 #size-cells = <0>;
414 };
415
179 clock-names = "ahb", "mod";
180 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
181 <&dma SUN4I_DMA_DEDICATED 26>;
182 dma-names = "rx", "tx";
183 status = "disabled";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 };
187
416 spi1: spi@01c06000 {
188 spi1: spi@1c06000 {
417 compatible = "allwinner,sun4i-a10-spi";
418 reg = <0x01c06000 0x1000>;
419 interrupts = <11>;
189 compatible = "allwinner,sun4i-a10-spi";
190 reg = <0x01c06000 0x1000>;
191 interrupts = <11>;
420 clocks = <&ahb_gates 21>, <&spi1_clk>;
192 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
421 clock-names = "ahb", "mod";
422 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
423 <&dma SUN4I_DMA_DEDICATED 8>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 };
429
193 clock-names = "ahb", "mod";
194 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
195 <&dma SUN4I_DMA_DEDICATED 8>;
196 dma-names = "rx", "tx";
197 status = "disabled";
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
430 mmc0: mmc@01c0f000 {
202 tve0: tv-encoder@1c0a000 {
203 compatible = "allwinner,sun4i-a10-tv-encoder";
204 reg = <0x01c0a000 0x1000>;
205 clocks = <&ccu CLK_AHB_TVE>;
206 resets = <&ccu RST_TVE>;
207 status = "disabled";
208
209 port {
210 #address-cells = <1>;
211 #size-cells = <0>;
212
213 tve0_in_tcon0: endpoint@0 {
214 reg = <0>;
215 remote-endpoint = <&tcon0_out_tve0>;
216 };
217 };
218 };
219
220 emac: ethernet@1c0b000 {
221 compatible = "allwinner,sun4i-a10-emac";
222 reg = <0x01c0b000 0x1000>;
223 interrupts = <55>;
224 clocks = <&ccu CLK_AHB_EMAC>;
225 allwinner,sram = <&emac_sram 1>;
226 status = "disabled";
227 };
228
229 mdio: mdio@1c0b080 {
230 compatible = "allwinner,sun4i-a10-mdio";
231 reg = <0x01c0b080 0x14>;
232 status = "disabled";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 };
236
237 tcon0: lcd-controller@1c0c000 {
238 compatible = "allwinner,sun5i-a13-tcon";
239 reg = <0x01c0c000 0x1000>;
240 interrupts = <44>;
241 resets = <&ccu RST_LCD>;
242 reset-names = "lcd";
243 clocks = <&ccu CLK_AHB_LCD>,
244 <&ccu CLK_TCON_CH0>,
245 <&ccu CLK_TCON_CH1>;
246 clock-names = "ahb",
247 "tcon-ch0",
248 "tcon-ch1";
249 clock-output-names = "tcon-pixel-clock";
250 status = "disabled";
251
252 ports {
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 tcon0_in: port@0 {
257 #address-cells = <1>;
258 #size-cells = <0>;
259 reg = <0>;
260
261 tcon0_in_be0: endpoint@0 {
262 reg = <0>;
263 remote-endpoint = <&be0_out_tcon0>;
264 };
265 };
266
267 tcon0_out: port@1 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 reg = <1>;
271
272 tcon0_out_tve0: endpoint@1 {
273 reg = <1>;
274 remote-endpoint = <&tve0_in_tcon0>;
275 allwinner,tcon-channel = <1>;
276 };
277 };
278 };
279 };
280
281 mmc0: mmc@1c0f000 {
431 compatible = "allwinner,sun5i-a13-mmc";
432 reg = <0x01c0f000 0x1000>;
282 compatible = "allwinner,sun5i-a13-mmc";
283 reg = <0x01c0f000 0x1000>;
433 clocks = <&ahb_gates 8>,
434 <&mmc0_clk 0>,
435 <&mmc0_clk 1>,
436 <&mmc0_clk 2>;
437 clock-names = "ahb",
438 "mmc",
439 "output",
440 "sample";
284 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
285 clock-names = "ahb", "mmc";
441 interrupts = <32>;
442 status = "disabled";
443 #address-cells = <1>;
444 #size-cells = <0>;
445 };
446
286 interrupts = <32>;
287 status = "disabled";
288 #address-cells = <1>;
289 #size-cells = <0>;
290 };
291
447 mmc1: mmc@01c10000 {
292 mmc1: mmc@1c10000 {
448 compatible = "allwinner,sun5i-a13-mmc";
449 reg = <0x01c10000 0x1000>;
293 compatible = "allwinner,sun5i-a13-mmc";
294 reg = <0x01c10000 0x1000>;
450 clocks = <&ahb_gates 9>,
451 <&mmc1_clk 0>,
452 <&mmc1_clk 1>,
453 <&mmc1_clk 2>;
454 clock-names = "ahb",
455 "mmc",
456 "output",
457 "sample";
295 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
296 clock-names = "ahb", "mmc";
458 interrupts = <33>;
459 status = "disabled";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 };
463
297 interrupts = <33>;
298 status = "disabled";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 };
302
464 mmc2: mmc@01c11000 {
303 mmc2: mmc@1c11000 {
465 compatible = "allwinner,sun5i-a13-mmc";
466 reg = <0x01c11000 0x1000>;
304 compatible = "allwinner,sun5i-a13-mmc";
305 reg = <0x01c11000 0x1000>;
467 clocks = <&ahb_gates 10>,
468 <&mmc2_clk 0>,
469 <&mmc2_clk 1>,
470 <&mmc2_clk 2>;
471 clock-names = "ahb",
472 "mmc",
473 "output",
474 "sample";
306 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
307 clock-names = "ahb", "mmc";
475 interrupts = <34>;
476 status = "disabled";
477 #address-cells = <1>;
478 #size-cells = <0>;
479 };
480
308 interrupts = <34>;
309 status = "disabled";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 };
313
481 usb_otg: usb@01c13000 {
314 usb_otg: usb@1c13000 {
482 compatible = "allwinner,sun4i-a10-musb";
483 reg = <0x01c13000 0x0400>;
315 compatible = "allwinner,sun4i-a10-musb";
316 reg = <0x01c13000 0x0400>;
484 clocks = <&ahb_gates 0>;
317 clocks = <&ccu CLK_AHB_OTG>;
485 interrupts = <38>;
486 interrupt-names = "mc";
487 phys = <&usbphy 0>;
488 phy-names = "usb";
489 extcon = <&usbphy 0>;
490 allwinner,sram = <&otg_sram 1>;
491 status = "disabled";
492 };
493
318 interrupts = <38>;
319 interrupt-names = "mc";
320 phys = <&usbphy 0>;
321 phy-names = "usb";
322 extcon = <&usbphy 0>;
323 allwinner,sram = <&otg_sram 1>;
324 status = "disabled";
325 };
326
494 usbphy: phy@01c13400 {
327 usbphy: phy@1c13400 {
495 #phy-cells = <1>;
496 compatible = "allwinner,sun5i-a13-usb-phy";
497 reg = <0x01c13400 0x10 0x01c14800 0x4>;
498 reg-names = "phy_ctrl", "pmu1";
328 #phy-cells = <1>;
329 compatible = "allwinner,sun5i-a13-usb-phy";
330 reg = <0x01c13400 0x10 0x01c14800 0x4>;
331 reg-names = "phy_ctrl", "pmu1";
499 clocks = <&usb_clk 8>;
332 clocks = <&ccu CLK_USB_PHY0>;
500 clock-names = "usb_phy";
333 clock-names = "usb_phy";
501 resets = <&usb_clk 0>, <&usb_clk 1>;
334 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
502 reset-names = "usb0_reset", "usb1_reset";
503 status = "disabled";
504 };
505
335 reset-names = "usb0_reset", "usb1_reset";
336 status = "disabled";
337 };
338
506 ehci0: usb@01c14000 {
339 ehci0: usb@1c14000 {
507 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
508 reg = <0x01c14000 0x100>;
509 interrupts = <39>;
340 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
341 reg = <0x01c14000 0x100>;
342 interrupts = <39>;
510 clocks = <&ahb_gates 1>;
343 clocks = <&ccu CLK_AHB_EHCI>;
511 phys = <&usbphy 1>;
512 phy-names = "usb";
513 status = "disabled";
514 };
515
344 phys = <&usbphy 1>;
345 phy-names = "usb";
346 status = "disabled";
347 };
348
516 ohci0: usb@01c14400 {
349 ohci0: usb@1c14400 {
517 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
518 reg = <0x01c14400 0x100>;
519 interrupts = <40>;
350 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
351 reg = <0x01c14400 0x100>;
352 interrupts = <40>;
520 clocks = <&usb_clk 6>, <&ahb_gates 2>;
353 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
521 phys = <&usbphy 1>;
522 phy-names = "usb";
523 status = "disabled";
524 };
525
354 phys = <&usbphy 1>;
355 phy-names = "usb";
356 status = "disabled";
357 };
358
526 spi2: spi@01c17000 {
359 crypto: crypto-engine@1c15000 {
360 compatible = "allwinner,sun5i-a13-crypto",
361 "allwinner,sun4i-a10-crypto";
362 reg = <0x01c15000 0x1000>;
363 interrupts = <54>;
364 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
365 clock-names = "ahb", "mod";
366 };
367
368 spi2: spi@1c17000 {
527 compatible = "allwinner,sun4i-a10-spi";
528 reg = <0x01c17000 0x1000>;
529 interrupts = <12>;
369 compatible = "allwinner,sun4i-a10-spi";
370 reg = <0x01c17000 0x1000>;
371 interrupts = <12>;
530 clocks = <&ahb_gates 22>, <&spi2_clk>;
372 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
531 clock-names = "ahb", "mod";
532 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
533 <&dma SUN4I_DMA_DEDICATED 28>;
534 dma-names = "rx", "tx";
535 status = "disabled";
536 #address-cells = <1>;
537 #size-cells = <0>;
538 };
539
373 clock-names = "ahb", "mod";
374 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
375 <&dma SUN4I_DMA_DEDICATED 28>;
376 dma-names = "rx", "tx";
377 status = "disabled";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 };
381
540 intc: interrupt-controller@01c20400 {
382 ccu: clock@1c20000 {
383 reg = <0x01c20000 0x400>;
384 clocks = <&osc24M>, <&osc32k>;
385 clock-names = "hosc", "losc";
386 #clock-cells = <1>;
387 #reset-cells = <1>;
388 };
389
390 intc: interrupt-controller@1c20400 {
541 compatible = "allwinner,sun4i-a10-ic";
542 reg = <0x01c20400 0x400>;
543 interrupt-controller;
544 #interrupt-cells = <1>;
545 };
546
391 compatible = "allwinner,sun4i-a10-ic";
392 reg = <0x01c20400 0x400>;
393 interrupt-controller;
394 #interrupt-cells = <1>;
395 };
396
547 pio: pinctrl@01c20800 {
397 pio: pinctrl@1c20800 {
548 reg = <0x01c20800 0x400>;
549 interrupts = <28>;
398 reg = <0x01c20800 0x400>;
399 interrupts = <28>;
550 clocks = <&apb0_gates 5>;
400 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
401 clock-names = "apb", "hosc", "losc";
551 gpio-controller;
552 interrupt-controller;
553 #interrupt-cells = <3>;
554 #gpio-cells = <3>;
555
402 gpio-controller;
403 interrupt-controller;
404 #interrupt-cells = <3>;
405 #gpio-cells = <3>;
406
407 emac_pins_a: emac0@0 {
408 pins = "PD6", "PD7", "PD10",
409 "PD11", "PD12", "PD13", "PD14",
410 "PD15", "PD18", "PD19", "PD20",
411 "PD21", "PD22", "PD23", "PD24",
412 "PD25", "PD26", "PD27";
413 function = "emac";
414 };
415
556 i2c0_pins_a: i2c0@0 {
416 i2c0_pins_a: i2c0@0 {
557 allwinner,pins = "PB0", "PB1";
558 allwinner,function = "i2c0";
559 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
560 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
417 pins = "PB0", "PB1";
418 function = "i2c0";
561 };
562
563 i2c1_pins_a: i2c1@0 {
419 };
420
421 i2c1_pins_a: i2c1@0 {
564 allwinner,pins = "PB15", "PB16";
565 allwinner,function = "i2c1";
566 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
567 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
422 pins = "PB15", "PB16";
423 function = "i2c1";
568 };
569
570 i2c2_pins_a: i2c2@0 {
424 };
425
426 i2c2_pins_a: i2c2@0 {
571 allwinner,pins = "PB17", "PB18";
572 allwinner,function = "i2c2";
573 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
574 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
427 pins = "PB17", "PB18";
428 function = "i2c2";
575 };
576
429 };
430
431 ir0_rx_pins_a: ir0@0 {
432 pins = "PB4";
433 function = "ir0";
434 };
435
436 lcd_rgb565_pins: lcd_rgb565@0 {
437 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
438 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
439 "PD19", "PD20", "PD21", "PD22", "PD23",
440 "PD24", "PD25", "PD26", "PD27";
441 function = "lcd0";
442 };
443
444 lcd_rgb666_pins: lcd_rgb666@0 {
445 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
446 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
447 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
448 "PD24", "PD25", "PD26", "PD27";
449 function = "lcd0";
450 };
451
577 mmc0_pins_a: mmc0@0 {
452 mmc0_pins_a: mmc0@0 {
578 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
579 "PF4", "PF5";
580 allwinner,function = "mmc0";
581 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
582 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
453 pins = "PF0", "PF1", "PF2", "PF3",
454 "PF4", "PF5";
455 function = "mmc0";
456 drive-strength = <30>;
457 bias-pull-up;
583 };
584
585 mmc2_pins_a: mmc2@0 {
458 };
459
460 mmc2_pins_a: mmc2@0 {
586 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
587 "PC10", "PC11", "PC12", "PC13",
588 "PC14", "PC15";
589 allwinner,function = "mmc2";
590 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
591 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
461 pins = "PC6", "PC7", "PC8", "PC9",
462 "PC10", "PC11", "PC12", "PC13",
463 "PC14", "PC15";
464 function = "mmc2";
465 drive-strength = <30>;
466 bias-pull-up;
592 };
593
467 };
468
469 mmc2_4bit_pins_a: mmc2-4bit@0 {
470 pins = "PC6", "PC7", "PC8", "PC9",
471 "PC10", "PC11";
472 function = "mmc2";
473 drive-strength = <30>;
474 bias-pull-up;
475 };
476
477 nand_pins_a: nand-base0@0 {
478 pins = "PC0", "PC1", "PC2",
479 "PC5", "PC8", "PC9", "PC10",
480 "PC11", "PC12", "PC13", "PC14",
481 "PC15";
482 function = "nand0";
483 };
484
485 nand_cs0_pins_a: nand-cs@0 {
486 pins = "PC4";
487 function = "nand0";
488 };
489
490 nand_rb0_pins_a: nand-rb@0 {
491 pins = "PC6";
492 function = "nand0";
493 };
494
495 spi2_pins_a: spi2@0 {
496 pins = "PE1", "PE2", "PE3";
497 function = "spi2";
498 };
499
500 spi2_cs0_pins_a: spi2-cs0@0 {
501 pins = "PE0";
502 function = "spi2";
503 };
504
505 uart1_pins_a: uart1@0 {
506 pins = "PE10", "PE11";
507 function = "uart1";
508 };
509
510 uart1_pins_b: uart1@1 {
511 pins = "PG3", "PG4";
512 function = "uart1";
513 };
514
515 uart2_pins_a: uart2@0 {
516 pins = "PD2", "PD3";
517 function = "uart2";
518 };
519
520 uart2_cts_rts_pins_a: uart2-cts-rts@0 {
521 pins = "PD4", "PD5";
522 function = "uart2";
523 };
524
594 uart3_pins_a: uart3@0 {
525 uart3_pins_a: uart3@0 {
595 allwinner,pins = "PG9", "PG10";
596 allwinner,function = "uart3";
597 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
598 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
526 pins = "PG9", "PG10";
527 function = "uart3";
599 };
600
528 };
529
601 uart3_pins_cts_rts_a: uart3-cts-rts@0 {
602 allwinner,pins = "PG11", "PG12";
603 allwinner,function = "uart3";
604 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
605 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
530 uart3_cts_rts_pins_a: uart3-cts-rts@0 {
531 pins = "PG11", "PG12";
532 function = "uart3";
606 };
607
608 pwm0_pins: pwm0 {
533 };
534
535 pwm0_pins: pwm0 {
609 allwinner,pins = "PB2";
610 allwinner,function = "pwm";
611 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
612 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
536 pins = "PB2";
537 function = "pwm";
613 };
614 };
615
538 };
539 };
540
616 timer@01c20c00 {
541 timer@1c20c00 {
617 compatible = "allwinner,sun4i-a10-timer";
618 reg = <0x01c20c00 0x90>;
619 interrupts = <22>;
542 compatible = "allwinner,sun4i-a10-timer";
543 reg = <0x01c20c00 0x90>;
544 interrupts = <22>;
620 clocks = <&osc24M>;
545 clocks = <&ccu CLK_HOSC>;
621 };
622
546 };
547
623 wdt: watchdog@01c20c90 {
548 wdt: watchdog@1c20c90 {
624 compatible = "allwinner,sun4i-a10-wdt";
625 reg = <0x01c20c90 0x10>;
626 };
627
549 compatible = "allwinner,sun4i-a10-wdt";
550 reg = <0x01c20c90 0x10>;
551 };
552
628 lradc: lradc@01c22800 {
553 ir0: ir@1c21800 {
554 compatible = "allwinner,sun4i-a10-ir";
555 clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
556 clock-names = "apb", "ir";
557 interrupts = <5>;
558 reg = <0x01c21800 0x40>;
559 status = "disabled";
560 };
561
562 lradc: lradc@1c22800 {
629 compatible = "allwinner,sun4i-a10-lradc-keys";
630 reg = <0x01c22800 0x100>;
631 interrupts = <31>;
632 status = "disabled";
633 };
634
563 compatible = "allwinner,sun4i-a10-lradc-keys";
564 reg = <0x01c22800 0x100>;
565 interrupts = <31>;
566 status = "disabled";
567 };
568
635 codec: codec@01c22c00 {
569 codec: codec@1c22c00 {
636 #sound-dai-cells = <0>;
637 compatible = "allwinner,sun4i-a10-codec";
638 reg = <0x01c22c00 0x40>;
639 interrupts = <30>;
570 #sound-dai-cells = <0>;
571 compatible = "allwinner,sun4i-a10-codec";
572 reg = <0x01c22c00 0x40>;
573 interrupts = <30>;
640 clocks = <&apb0_gates 0>, <&codec_clk>;
574 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
641 clock-names = "apb", "codec";
642 dmas = <&dma SUN4I_DMA_NORMAL 19>,
643 <&dma SUN4I_DMA_NORMAL 19>;
644 dma-names = "rx", "tx";
645 status = "disabled";
646 };
647
575 clock-names = "apb", "codec";
576 dmas = <&dma SUN4I_DMA_NORMAL 19>,
577 <&dma SUN4I_DMA_NORMAL 19>;
578 dma-names = "rx", "tx";
579 status = "disabled";
580 };
581
648 sid: eeprom@01c23800 {
582 sid: eeprom@1c23800 {
649 compatible = "allwinner,sun4i-a10-sid";
650 reg = <0x01c23800 0x10>;
651 };
652
583 compatible = "allwinner,sun4i-a10-sid";
584 reg = <0x01c23800 0x10>;
585 };
586
653 rtp: rtp@01c25000 {
587 rtp: rtp@1c25000 {
654 compatible = "allwinner,sun5i-a13-ts";
655 reg = <0x01c25000 0x100>;
656 interrupts = <29>;
657 #thermal-sensor-cells = <0>;
658 };
659
588 compatible = "allwinner,sun5i-a13-ts";
589 reg = <0x01c25000 0x100>;
590 interrupts = <29>;
591 #thermal-sensor-cells = <0>;
592 };
593
660 uart1: serial@01c28400 {
594 uart0: serial@1c28000 {
661 compatible = "snps,dw-apb-uart";
595 compatible = "snps,dw-apb-uart";
596 reg = <0x01c28000 0x400>;
597 interrupts = <1>;
598 reg-shift = <2>;
599 reg-io-width = <4>;
600 clocks = <&ccu CLK_APB1_UART0>;
601 status = "disabled";
602 };
603
604 uart1: serial@1c28400 {
605 compatible = "snps,dw-apb-uart";
662 reg = <0x01c28400 0x400>;
663 interrupts = <2>;
664 reg-shift = <2>;
665 reg-io-width = <4>;
606 reg = <0x01c28400 0x400>;
607 interrupts = <2>;
608 reg-shift = <2>;
609 reg-io-width = <4>;
666 clocks = <&apb1_gates 17>;
610 clocks = <&ccu CLK_APB1_UART1>;
667 status = "disabled";
668 };
669
611 status = "disabled";
612 };
613
670 uart3: serial@01c28c00 {
614 uart2: serial@1c28800 {
671 compatible = "snps,dw-apb-uart";
615 compatible = "snps,dw-apb-uart";
616 reg = <0x01c28800 0x400>;
617 interrupts = <3>;
618 reg-shift = <2>;
619 reg-io-width = <4>;
620 clocks = <&ccu CLK_APB1_UART2>;
621 status = "disabled";
622 };
623
624 uart3: serial@1c28c00 {
625 compatible = "snps,dw-apb-uart";
672 reg = <0x01c28c00 0x400>;
673 interrupts = <4>;
674 reg-shift = <2>;
675 reg-io-width = <4>;
626 reg = <0x01c28c00 0x400>;
627 interrupts = <4>;
628 reg-shift = <2>;
629 reg-io-width = <4>;
676 clocks = <&apb1_gates 19>;
630 clocks = <&ccu CLK_APB1_UART3>;
677 status = "disabled";
678 };
679
631 status = "disabled";
632 };
633
680 i2c0: i2c@01c2ac00 {
634 i2c0: i2c@1c2ac00 {
681 compatible = "allwinner,sun4i-a10-i2c";
682 reg = <0x01c2ac00 0x400>;
683 interrupts = <7>;
635 compatible = "allwinner,sun4i-a10-i2c";
636 reg = <0x01c2ac00 0x400>;
637 interrupts = <7>;
684 clocks = <&apb1_gates 0>;
638 clocks = <&ccu CLK_APB1_I2C0>;
685 status = "disabled";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 };
689
639 status = "disabled";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 };
643
690 i2c1: i2c@01c2b000 {
644 i2c1: i2c@1c2b000 {
691 compatible = "allwinner,sun4i-a10-i2c";
692 reg = <0x01c2b000 0x400>;
693 interrupts = <8>;
645 compatible = "allwinner,sun4i-a10-i2c";
646 reg = <0x01c2b000 0x400>;
647 interrupts = <8>;
694 clocks = <&apb1_gates 1>;
648 clocks = <&ccu CLK_APB1_I2C1>;
695 status = "disabled";
696 #address-cells = <1>;
697 #size-cells = <0>;
698 };
699
649 status = "disabled";
650 #address-cells = <1>;
651 #size-cells = <0>;
652 };
653
700 i2c2: i2c@01c2b400 {
654 i2c2: i2c@1c2b400 {
701 compatible = "allwinner,sun4i-a10-i2c";
702 reg = <0x01c2b400 0x400>;
703 interrupts = <9>;
655 compatible = "allwinner,sun4i-a10-i2c";
656 reg = <0x01c2b400 0x400>;
657 interrupts = <9>;
704 clocks = <&apb1_gates 2>;
658 clocks = <&ccu CLK_APB1_I2C2>;
705 status = "disabled";
706 #address-cells = <1>;
707 #size-cells = <0>;
708 };
709
659 status = "disabled";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 };
663
710 timer@01c60000 {
664 timer@1c60000 {
711 compatible = "allwinner,sun5i-a13-hstimer";
712 reg = <0x01c60000 0x1000>;
713 interrupts = <82>, <83>;
665 compatible = "allwinner,sun5i-a13-hstimer";
666 reg = <0x01c60000 0x1000>;
667 interrupts = <82>, <83>;
714 clocks = <&ahb_gates 28>;
668 clocks = <&ccu CLK_AHB_HSTIMER>;
715 };
669 };
670
671 fe0: display-frontend@1e00000 {
672 compatible = "allwinner,sun5i-a13-display-frontend";
673 reg = <0x01e00000 0x20000>;
674 interrupts = <47>;
675 clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
676 <&ccu CLK_DRAM_DE_FE>;
677 clock-names = "ahb", "mod",
678 "ram";
679 resets = <&ccu RST_DE_FE>;
680 status = "disabled";
681
682 ports {
683 #address-cells = <1>;
684 #size-cells = <0>;
685
686 fe0_out: port@1 {
687 #address-cells = <1>;
688 #size-cells = <0>;
689 reg = <1>;
690
691 fe0_out_be0: endpoint@0 {
692 reg = <0>;
693 remote-endpoint = <&be0_in_fe0>;
694 };
695 };
696 };
697 };
698
699 be0: display-backend@1e60000 {
700 compatible = "allwinner,sun5i-a13-display-backend";
701 reg = <0x01e60000 0x10000>;
702 interrupts = <47>;
703 clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
704 <&ccu CLK_DRAM_DE_BE>;
705 clock-names = "ahb", "mod",
706 "ram";
707 resets = <&ccu RST_DE_BE>;
708 status = "disabled";
709
710 assigned-clocks = <&ccu CLK_DE_BE>;
711 assigned-clock-rates = <300000000>;
712
713 ports {
714 #address-cells = <1>;
715 #size-cells = <0>;
716
717 be0_in: port@0 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 reg = <0>;
721
722 be0_in_fe0: endpoint@0 {
723 reg = <0>;
724 remote-endpoint = <&fe0_out_be0>;
725 };
726 };
727
728 be0_out: port@1 {
729 #address-cells = <1>;
730 #size-cells = <0>;
731 reg = <1>;
732
733 be0_out_tcon0: endpoint@0 {
734 reg = <0>;
735 remote-endpoint = <&tcon0_in_be0>;
736 };
737 };
738 };
739 };
716 };
717};
740 };
741};