| README (f8cb101e1e3f5ee2007b78b6b12e24120385aeac) | README (4516ff816084605990115d127df97950c23e389c) |
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| 1# 2# (C) Copyright 2000 - 2013 3# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8Summary: --- 4870 unchanged lines hidden (view full) --- 4879 header files or board specific files. 4880 4881- CONFIG_FSL_DDR_INTERACTIVE 4882 Enable interactive DDR debugging. See doc/README.fsl-ddr. 4883 4884- CONFIG_FSL_DDR_SYNC_REFRESH 4885 Enable sync of refresh for multiple controllers. 4886 | 1# 2# (C) Copyright 2000 - 2013 3# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8Summary: --- 4870 unchanged lines hidden (view full) --- 4879 header files or board specific files. 4880 4881- CONFIG_FSL_DDR_INTERACTIVE 4882 Enable interactive DDR debugging. See doc/README.fsl-ddr. 4883 4884- CONFIG_FSL_DDR_SYNC_REFRESH 4885 Enable sync of refresh for multiple controllers. 4886 |
| 4887- CONFIG_FSL_DDR_BIST 4888 Enable built-in memory test for Freescale DDR controllers. 4889 |
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| 4887- CONFIG_SYS_83XX_DDR_USES_CS0 4888 Only for 83xx systems. If specified, then DDR should 4889 be configured using CS0 and CS1 instead of CS2 and CS3. 4890 4891- CONFIG_ETHER_ON_FEC[12] 4892 Define to enable FEC[12] on a 8xx series processor. 4893 4894- CONFIG_FEC[12]_PHY --- 1778 unchanged lines hidden --- | 4890- CONFIG_SYS_83XX_DDR_USES_CS0 4891 Only for 83xx systems. If specified, then DDR should 4892 be configured using CS0 and CS1 instead of CS2 and CS3. 4893 4894- CONFIG_ETHER_ON_FEC[12] 4895 Define to enable FEC[12] on a 8xx series processor. 4896 4897- CONFIG_FEC[12]_PHY --- 1778 unchanged lines hidden --- |