| README (dcf1d774bf5c2612538658eac01931895b7a805f) | README (34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85) |
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| 1# 2# (C) Copyright 2000 - 2013 3# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8Summary: --- 444 unchanged lines hidden (view full) --- 453 Freescale DDR1 controller. 454 455 CONFIG_SYS_FSL_DDRC_GEN2 456 Freescale DDR2 controller. 457 458 CONFIG_SYS_FSL_DDRC_GEN3 459 Freescale DDR3 controller. 460 | 1# 2# (C) Copyright 2000 - 2013 3# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8Summary: --- 444 unchanged lines hidden (view full) --- 453 Freescale DDR1 controller. 454 455 CONFIG_SYS_FSL_DDRC_GEN2 456 Freescale DDR2 controller. 457 458 CONFIG_SYS_FSL_DDRC_GEN3 459 Freescale DDR3 controller. 460 |
| 461 CONFIG_SYS_FSL_DDRC_GEN4 462 Freescale DDR4 controller. 463 |
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| 461 CONFIG_SYS_FSL_DDRC_ARM_GEN3 462 Freescale DDR3 controller for ARM-based SoCs. 463 464 CONFIG_SYS_FSL_DDR1 465 Board config to use DDR1. It can be enabled for SoCs with 466 Freescale DDR1 or DDR2 controllers, depending on the board 467 implemetation. 468 469 CONFIG_SYS_FSL_DDR2 470 Board config to use DDR2. It can be eanbeld for SoCs with 471 Freescale DDR2 or DDR3 controllers, depending on the board 472 implementation. 473 474 CONFIG_SYS_FSL_DDR3 475 Board config to use DDR3. It can be enabled for SoCs with | 464 CONFIG_SYS_FSL_DDRC_ARM_GEN3 465 Freescale DDR3 controller for ARM-based SoCs. 466 467 CONFIG_SYS_FSL_DDR1 468 Board config to use DDR1. It can be enabled for SoCs with 469 Freescale DDR1 or DDR2 controllers, depending on the board 470 implemetation. 471 472 CONFIG_SYS_FSL_DDR2 473 Board config to use DDR2. It can be eanbeld for SoCs with 474 Freescale DDR2 or DDR3 controllers, depending on the board 475 implementation. 476 477 CONFIG_SYS_FSL_DDR3 478 Board config to use DDR3. It can be enabled for SoCs with |
| 476 Freescale DDR3 controllers. | 479 Freescale DDR3 or DDR3L controllers. |
| 477 | 480 |
| 481 CONFIG_SYS_FSL_DDR3L 482 Board config to use DDR3L. It can be enabled for SoCs with 483 DDR3L controllers. 484 485 CONFIG_SYS_FSL_DDR4 486 Board config to use DDR4. It can be enabled for SoCs with 487 DDR4 controllers. 488 |
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| 478 CONFIG_SYS_FSL_IFC_BE 479 Defines the IFC controller register space as Big Endian 480 481 CONFIG_SYS_FSL_IFC_LE 482 Defines the IFC controller register space as Little Endian 483 484 CONFIG_SYS_FSL_PBL_PBI 485 It enables addition of RCW (Power on reset configuration) in built image. --- 5653 unchanged lines hidden --- | 489 CONFIG_SYS_FSL_IFC_BE 490 Defines the IFC controller register space as Big Endian 491 492 CONFIG_SYS_FSL_IFC_LE 493 Defines the IFC controller register space as Little Endian 494 495 CONFIG_SYS_FSL_PBL_PBI 496 It enables addition of RCW (Power on reset configuration) in built image. --- 5653 unchanged lines hidden --- |