tcg-op.c - OpenGrok cross reference for /openbmc/qemu/tcg/tcg-op.c

1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights

--- 2700 unchanged lines hidden (view full) ---

2709 gen_helper_lookup_tb_ptr(ptr, cpu_env);
2710 tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
2711 tcg_temp_free_ptr(ptr);
2712 } else {
2713 tcg_gen_exit_tb(NULL, 0);
2714 }
2715}
2716

2717static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)

2717static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)

2718{
2719 /* Trigger the asserts within as early as possible. */
2720 (void)get_alignment_bits(op);
2721
2722 switch (op & MO_SIZE) {
2723 case MO_8:
2724 op &= ~MO_BSWAP;
2725 break;

--- 12 unchanged lines hidden (view full) ---

2738 }
2739 if (st) {
2740 op &= ~MO_SIGN;
2741 }
2742 return op;
2743}
2744
2745static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,

2746 TCGMemOp memop, TCGArg idx)

2746 MemOp memop, TCGArg idx)

2747{
2748 TCGMemOpIdx oi = make_memop_idx(memop, idx);
2749#if TARGET_LONG_BITS == 32
2750 tcg_gen_op3i_i32(opc, val, addr, oi);
2751#else
2752 if (TCG_TARGET_REG_BITS == 32) {
2753 tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi);
2754 } else {
2755 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_i64_arg(addr), oi);
2756 }
2757#endif
2758}
2759
2760static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,

2761 TCGMemOp memop, TCGArg idx)

2761 MemOp memop, TCGArg idx)

2762{
2763 TCGMemOpIdx oi = make_memop_idx(memop, idx);
2764#if TARGET_LONG_BITS == 32
2765 if (TCG_TARGET_REG_BITS == 32) {
2766 tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
2767 } else {
2768 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_i32_arg(addr), oi);
2769 }

--- 13 unchanged lines hidden (view full) ---

2783 type &= TCG_GUEST_DEFAULT_MO;
2784#endif
2785 type &= ~TCG_TARGET_DEFAULT_MO;
2786 if (type) {
2787 tcg_gen_mb(type | TCG_BAR_SC);
2788 }
2789}
2790

2791void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)

2791void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)

2792{

2793 TCGMemOp orig_memop;

2793 MemOp orig_memop;

2794
2795 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
2796 memop = tcg_canonicalize_memop(memop, 0, 0);
2797 trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env,
2798 addr, trace_mem_get_info(memop, 0));
2799
2800 orig_memop = memop;
2801 if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {

--- 18 unchanged lines hidden (view full) ---

2820 tcg_gen_bswap32_i32(val, val);
2821 break;
2822 default:
2823 g_assert_not_reached();
2824 }
2825 }
2826}
2827

2828void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)

2828void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)

2829{
2830 TCGv_i32 swap = NULL;
2831
2832 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
2833 memop = tcg_canonicalize_memop(memop, 0, 1);
2834 trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env,
2835 addr, trace_mem_get_info(memop, 1));
2836

--- 16 unchanged lines hidden (view full) ---

2853
2854 gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
2855
2856 if (swap) {
2857 tcg_temp_free_i32(swap);
2858 }
2859}
2860

2861void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)

2861void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)

2862{

2863 TCGMemOp orig_memop;

2863 MemOp orig_memop;

2864
2865 if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
2866 tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
2867 if (memop & MO_SIGN) {
2868 tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);
2869 } else {
2870 tcg_gen_movi_i32(TCGV_HIGH(val), 0);
2871 }

--- 34 unchanged lines hidden (view full) ---

2906 tcg_gen_bswap64_i64(val, val);
2907 break;
2908 default:
2909 g_assert_not_reached();
2910 }
2911 }
2912}
2913

2914void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)

2914void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)

2915{
2916 TCGv_i64 swap = NULL;
2917
2918 if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
2919 tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
2920 return;
2921 }
2922

--- 25 unchanged lines hidden (view full) ---

2948
2949 gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
2950
2951 if (swap) {
2952 tcg_temp_free_i64(swap);
2953 }
2954}
2955

2956static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)

2956static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc)

2957{
2958 switch (opc & MO_SSIZE) {
2959 case MO_SB:
2960 tcg_gen_ext8s_i32(ret, val);
2961 break;
2962 case MO_UB:
2963 tcg_gen_ext8u_i32(ret, val);
2964 break;

--- 4 unchanged lines hidden (view full) ---

2969 tcg_gen_ext16u_i32(ret, val);
2970 break;
2971 default:
2972 tcg_gen_mov_i32(ret, val);
2973 break;
2974 }
2975}
2976

2977static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc)

2977static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc)

2978{
2979 switch (opc & MO_SSIZE) {
2980 case MO_SB:
2981 tcg_gen_ext8s_i64(ret, val);
2982 break;
2983 case MO_UB:
2984 tcg_gen_ext8u_i64(ret, val);
2985 break;

--- 43 unchanged lines hidden (view full) ---

3029 [MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
3030 [MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,
3031 [MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,
3032 WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le)
3033 WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be)
3034};
3035
3036void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,

3037 TCGv_i32 newv, TCGArg idx, TCGMemOp memop)

3037 TCGv_i32 newv, TCGArg idx, MemOp memop)

3038{
3039 memop = tcg_canonicalize_memop(memop, 0, 0);
3040
3041 if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) {
3042 TCGv_i32 t1 = tcg_temp_new_i32();
3043 TCGv_i32 t2 = tcg_temp_new_i32();
3044
3045 tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE);

--- 27 unchanged lines hidden (view full) ---

3073
3074 if (memop & MO_SIGN) {
3075 tcg_gen_ext_i32(retv, retv, memop);
3076 }
3077 }
3078}
3079
3080void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,

3081 TCGv_i64 newv, TCGArg idx, TCGMemOp memop)

3081 TCGv_i64 newv, TCGArg idx, MemOp memop)

3082{
3083 memop = tcg_canonicalize_memop(memop, 1, 0);
3084
3085 if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) {
3086 TCGv_i64 t1 = tcg_temp_new_i64();
3087 TCGv_i64 t2 = tcg_temp_new_i64();
3088
3089 tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE);

--- 47 unchanged lines hidden (view full) ---

3137
3138 if (memop & MO_SIGN) {
3139 tcg_gen_ext_i64(retv, retv, memop);
3140 }
3141 }
3142}
3143
3144static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,

3145 TCGArg idx, TCGMemOp memop, bool new_val,

3145 TCGArg idx, MemOp memop, bool new_val,

3146 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
3147{
3148 TCGv_i32 t1 = tcg_temp_new_i32();
3149 TCGv_i32 t2 = tcg_temp_new_i32();
3150
3151 memop = tcg_canonicalize_memop(memop, 0, 0);
3152
3153 tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
3154 gen(t2, t1, val);
3155 tcg_gen_qemu_st_i32(t2, addr, idx, memop);
3156
3157 tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop);
3158 tcg_temp_free_i32(t1);
3159 tcg_temp_free_i32(t2);
3160}
3161
3162static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,

3163 TCGArg idx, TCGMemOp memop, void * const table[])

3163 TCGArg idx, MemOp memop, void * const table[])

3164{
3165 gen_atomic_op_i32 gen;
3166
3167 memop = tcg_canonicalize_memop(memop, 0, 0);
3168
3169 gen = table[memop & (MO_SIZE | MO_BSWAP)];
3170 tcg_debug_assert(gen != NULL);
3171

--- 8 unchanged lines hidden (view full) ---

3180#endif
3181
3182 if (memop & MO_SIGN) {
3183 tcg_gen_ext_i32(ret, ret, memop);
3184 }
3185}
3186
3187static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,

3188 TCGArg idx, TCGMemOp memop, bool new_val,

3188 TCGArg idx, MemOp memop, bool new_val,

3189 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
3190{
3191 TCGv_i64 t1 = tcg_temp_new_i64();
3192 TCGv_i64 t2 = tcg_temp_new_i64();
3193
3194 memop = tcg_canonicalize_memop(memop, 1, 0);
3195
3196 tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN);
3197 gen(t2, t1, val);
3198 tcg_gen_qemu_st_i64(t2, addr, idx, memop);
3199
3200 tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop);
3201 tcg_temp_free_i64(t1);
3202 tcg_temp_free_i64(t2);
3203}
3204
3205static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,

3206 TCGArg idx, TCGMemOp memop, void * const table[])

3206 TCGArg idx, MemOp memop, void * const table[])

3207{
3208 memop = tcg_canonicalize_memop(memop, 1, 0);
3209
3210 if ((memop & MO_SIZE) == MO_64) {
3211#ifdef CONFIG_ATOMIC64
3212 gen_atomic_op_i64 gen;
3213
3214 gen = table[memop & (MO_SIZE | MO_BSWAP)];

--- 37 unchanged lines hidden (view full) ---

3252 [MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \
3253 [MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \
3254 [MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \
3255 [MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \
3256 WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le) \
3257 WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \
3258}; \
3259void tcg_gen_atomic_##NAME##_i32 \

3260 (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \

3260 (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \

3261{ \
3262 if (tcg_ctx->tb_cflags & CF_PARALLEL) { \
3263 do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
3264 } else { \
3265 do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \
3266 tcg_gen_##OP##_i32); \
3267 } \
3268} \
3269void tcg_gen_atomic_##NAME##_i64 \

3270 (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \

3270 (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \