tcg-target.c.inc (a429ee2978a1bb81cfb737e382a47c119a2c0886) tcg-target.c.inc (ae77bbe5747dc655bed213006798f9b07e2f79bf)
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy

--- 256 unchanged lines hidden (view full) ---

265 RX_STC = 0x42,
266 RX_STH = 0x40,
267
268 VRIa_VGBM = 0xe744,
269 VRIa_VREPI = 0xe745,
270 VRIb_VGM = 0xe746,
271 VRIc_VREP = 0xe74d,
272
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy

--- 256 unchanged lines hidden (view full) ---

265 RX_STC = 0x42,
266 RX_STH = 0x40,
267
268 VRIa_VGBM = 0xe744,
269 VRIa_VREPI = 0xe745,
270 VRIb_VGM = 0xe746,
271 VRIc_VREP = 0xe74d,
272
273 VRRa_VLC = 0xe7de,
274 VRRa_VLP = 0xe7df,
273 VRRa_VLR = 0xe756,
274 VRRc_VA = 0xe7f3,
275 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
276 VRRc_VCH = 0xe7fb, /* " */
277 VRRc_VCHL = 0xe7f9, /* " */
278 VRRc_VN = 0xe768,
275 VRRa_VLR = 0xe756,
276 VRRc_VA = 0xe7f3,
277 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
278 VRRc_VCH = 0xe7fb, /* " */
279 VRRc_VCHL = 0xe7f9, /* " */
280 VRRc_VN = 0xe768,
281 VRRc_VNC = 0xe769,
282 VRRc_VNO = 0xe76b,
279 VRRc_VO = 0xe76a,
283 VRRc_VO = 0xe76a,
284 VRRc_VOC = 0xe76f,
280 VRRc_VS = 0xe7f7,
281 VRRc_VX = 0xe76d,
282 VRRf_VLVGP = 0xe762,
283
284 VRSb_VLVG = 0xe722,
285 VRSc_VLGV = 0xe721,
286
287 VRX_VL = 0xe706,

--- 2376 unchanged lines hidden (view full) ---

2664 break;
2665 case INDEX_op_st_vec:
2666 tcg_out_st(s, type, a0, a1, a2);
2667 break;
2668 case INDEX_op_dupm_vec:
2669 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
2670 break;
2671
285 VRRc_VS = 0xe7f7,
286 VRRc_VX = 0xe76d,
287 VRRf_VLVGP = 0xe762,
288
289 VRSb_VLVG = 0xe722,
290 VRSc_VLGV = 0xe721,
291
292 VRX_VL = 0xe706,

--- 2376 unchanged lines hidden (view full) ---

2669 break;
2670 case INDEX_op_st_vec:
2671 tcg_out_st(s, type, a0, a1, a2);
2672 break;
2673 case INDEX_op_dupm_vec:
2674 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
2675 break;
2676
2677 case INDEX_op_abs_vec:
2678 tcg_out_insn(s, VRRa, VLP, a0, a1, vece);
2679 break;
2680 case INDEX_op_neg_vec:
2681 tcg_out_insn(s, VRRa, VLC, a0, a1, vece);
2682 break;
2683 case INDEX_op_not_vec:
2684 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0);
2685 break;
2686
2672 case INDEX_op_add_vec:
2673 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
2674 break;
2675 case INDEX_op_sub_vec:
2676 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece);
2677 break;
2678 case INDEX_op_and_vec:
2679 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
2680 break;
2687 case INDEX_op_add_vec:
2688 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
2689 break;
2690 case INDEX_op_sub_vec:
2691 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece);
2692 break;
2693 case INDEX_op_and_vec:
2694 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
2695 break;
2696 case INDEX_op_andc_vec:
2697 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
2698 break;
2681 case INDEX_op_or_vec:
2682 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
2683 break;
2699 case INDEX_op_or_vec:
2700 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
2701 break;
2702 case INDEX_op_orc_vec:
2703 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0);
2704 break;
2684 case INDEX_op_xor_vec:
2685 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
2686 break;
2687
2688 case INDEX_op_cmp_vec:
2689 switch ((TCGCond)args[3]) {
2690 case TCG_COND_EQ:
2691 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece);

--- 14 unchanged lines hidden (view full) ---

2706 default:
2707 g_assert_not_reached();
2708 }
2709}
2710
2711int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2712{
2713 switch (opc) {
2705 case INDEX_op_xor_vec:
2706 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
2707 break;
2708
2709 case INDEX_op_cmp_vec:
2710 switch ((TCGCond)args[3]) {
2711 case TCG_COND_EQ:
2712 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece);

--- 14 unchanged lines hidden (view full) ---

2727 default:
2728 g_assert_not_reached();
2729 }
2730}
2731
2732int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2733{
2734 switch (opc) {
2735 case INDEX_op_abs_vec:
2714 case INDEX_op_add_vec:
2715 case INDEX_op_and_vec:
2736 case INDEX_op_add_vec:
2737 case INDEX_op_and_vec:
2738 case INDEX_op_andc_vec:
2739 case INDEX_op_neg_vec:
2740 case INDEX_op_not_vec:
2716 case INDEX_op_or_vec:
2741 case INDEX_op_or_vec:
2742 case INDEX_op_orc_vec:
2717 case INDEX_op_sub_vec:
2718 case INDEX_op_xor_vec:
2719 return 1;
2720 case INDEX_op_cmp_vec:
2721 return -1;
2722 default:
2723 return 0;
2724 }

--- 213 unchanged lines hidden (view full) ---

2938
2939 case INDEX_op_st_vec:
2940 return C_O0_I2(v, r);
2941 case INDEX_op_ld_vec:
2942 case INDEX_op_dupm_vec:
2943 return C_O1_I1(v, r);
2944 case INDEX_op_dup_vec:
2945 return C_O1_I1(v, vr);
2743 case INDEX_op_sub_vec:
2744 case INDEX_op_xor_vec:
2745 return 1;
2746 case INDEX_op_cmp_vec:
2747 return -1;
2748 default:
2749 return 0;
2750 }

--- 213 unchanged lines hidden (view full) ---

2964
2965 case INDEX_op_st_vec:
2966 return C_O0_I2(v, r);
2967 case INDEX_op_ld_vec:
2968 case INDEX_op_dupm_vec:
2969 return C_O1_I1(v, r);
2970 case INDEX_op_dup_vec:
2971 return C_O1_I1(v, vr);
2972 case INDEX_op_abs_vec:
2973 case INDEX_op_neg_vec:
2974 case INDEX_op_not_vec:
2975 return C_O1_I1(v, v);
2946 case INDEX_op_add_vec:
2947 case INDEX_op_sub_vec:
2948 case INDEX_op_and_vec:
2976 case INDEX_op_add_vec:
2977 case INDEX_op_sub_vec:
2978 case INDEX_op_and_vec:
2979 case INDEX_op_andc_vec:
2949 case INDEX_op_or_vec:
2980 case INDEX_op_or_vec:
2981 case INDEX_op_orc_vec:
2950 case INDEX_op_xor_vec:
2951 case INDEX_op_cmp_vec:
2952 return C_O1_I2(v, v, v);
2953
2954 default:
2955 g_assert_not_reached();
2956 }
2957}

--- 193 unchanged lines hidden --- 		2982 case INDEX_op_xor_vec:
2983 case INDEX_op_cmp_vec:
2984 return C_O1_I2(v, v, v);
2985
2986 default:
2987 g_assert_not_reached();
2988 }
2989}

--- 193 unchanged lines hidden ---