tcg-target.c.inc (e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7) tcg-target.c.inc (d2f3066eb2af5d6867974493833834e2aaa427f7)
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *

--- 1448 unchanged lines hidden (view full) ---

1457 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1458 break;
1459 case INDEX_op_remu_i64:
1460 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1461 break;
1462
1463 case INDEX_op_shl_i32:
1464 if (c2) {
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *

--- 1448 unchanged lines hidden (view full) ---

1457 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1458 break;
1459 case INDEX_op_remu_i64:
1460 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1461 break;
1462
1463 case INDEX_op_shl_i32:
1464 if (c2) {
1465 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
1465 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
1466 } else {
1467 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1468 }
1469 break;
1470 case INDEX_op_shl_i64:
1471 if (c2) {
1466 } else {
1467 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1468 }
1469 break;
1470 case INDEX_op_shl_i64:
1471 if (c2) {
1472 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
1472 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
1473 } else {
1474 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1475 }
1476 break;
1477
1478 case INDEX_op_shr_i32:
1479 if (c2) {
1473 } else {
1474 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1475 }
1476 break;
1477
1478 case INDEX_op_shr_i32:
1479 if (c2) {
1480 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
1480 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
1481 } else {
1482 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1483 }
1484 break;
1485 case INDEX_op_shr_i64:
1486 if (c2) {
1481 } else {
1482 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1483 }
1484 break;
1485 case INDEX_op_shr_i64:
1486 if (c2) {
1487 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
1487 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
1488 } else {
1489 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1490 }
1491 break;
1492
1493 case INDEX_op_sar_i32:
1494 if (c2) {
1488 } else {
1489 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1490 }
1491 break;
1492
1493 case INDEX_op_sar_i32:
1494 if (c2) {
1495 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
1495 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
1496 } else {
1497 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1498 }
1499 break;
1500 case INDEX_op_sar_i64:
1501 if (c2) {
1496 } else {
1497 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1498 }
1499 break;
1500 case INDEX_op_sar_i64:
1501 if (c2) {
1502 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
1502 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
1503 } else {
1504 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1505 }
1506 break;
1507
1508 case INDEX_op_add2_i32:
1509 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1510 const_args[4], const_args[5], false, true);

--- 403 unchanged lines hidden --- 		1503 } else {
1504 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1505 }
1506 break;
1507
1508 case INDEX_op_add2_i32:
1509 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1510 const_args[4], const_args[5], false, true);

--- 403 unchanged lines hidden ---