tcg-target.c.inc (6a6d772e30d62e209587ef341df243e9789f5a9f) tcg-target.c.inc (5e3d0c199f4edf4ecdf8100464da441c60ce36e3)
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *

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108 TCG_REG_A2,
109 TCG_REG_A3,
110 TCG_REG_A4,
111 TCG_REG_A5,
112 TCG_REG_A6,
113 TCG_REG_A7,
114};
115
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
7 * Copyright (c) 2008 Fabrice Bellard
8 *

--- 99 unchanged lines hidden (view full) ---

108 TCG_REG_A2,
109 TCG_REG_A3,
110 TCG_REG_A4,
111 TCG_REG_A5,
112 TCG_REG_A6,
113 TCG_REG_A7,
114};
115
116static const int tcg_target_call_oarg_regs[] = {
117 TCG_REG_A0,
118 TCG_REG_A1,
119};
116static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
117{
118 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
119 tcg_debug_assert(slot >= 0 && slot <= 1);
120 return TCG_REG_A0 + slot;
121}
120
121#define TCG_CT_CONST_ZERO 0x100
122#define TCG_CT_CONST_S12 0x200
123#define TCG_CT_CONST_N12 0x400
124#define TCG_CT_CONST_M12 0x800
125
126#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
127/*

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123#define TCG_CT_CONST_ZERO 0x100
124#define TCG_CT_CONST_S12 0x200
125#define TCG_CT_CONST_N12 0x400
126#define TCG_CT_CONST_M12 0x800
127
128#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
129/*

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