tcg-target.c.inc (6a6d772e30d62e209587ef341df243e9789f5a9f) tcg-target.c.inc (5e3d0c199f4edf4ecdf8100464da441c60ce36e3)
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5 *
6 * Based on tcg/riscv/tcg-target.c.inc
7 *
8 * Copyright (c) 2018 SiFive, Inc

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109 TCG_REG_A2,
110 TCG_REG_A3,
111 TCG_REG_A4,
112 TCG_REG_A5,
113 TCG_REG_A6,
114 TCG_REG_A7,
115};
116
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5 *
6 * Based on tcg/riscv/tcg-target.c.inc
7 *
8 * Copyright (c) 2018 SiFive, Inc

--- 100 unchanged lines hidden (view full) ---

109 TCG_REG_A2,
110 TCG_REG_A3,
111 TCG_REG_A4,
112 TCG_REG_A5,
113 TCG_REG_A6,
114 TCG_REG_A7,
115};
116
117static const int tcg_target_call_oarg_regs[] = {
118 TCG_REG_A0,
119 TCG_REG_A1,
120};
117static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
118{
119 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
120 tcg_debug_assert(slot >= 0 && slot <= 1);
121 return TCG_REG_A0 + slot;
122}
121
122#ifndef CONFIG_SOFTMMU
123#define USE_GUEST_BASE (guest_base != 0)
124#define TCG_GUEST_BASE_REG TCG_REG_S1
125#endif
126
127#define TCG_CT_CONST_ZERO 0x100
128#define TCG_CT_CONST_S12 0x200

--- 1786 unchanged lines hidden --- 		123
124#ifndef CONFIG_SOFTMMU
125#define USE_GUEST_BASE (guest_base != 0)
126#define TCG_GUEST_BASE_REG TCG_REG_S1
127#endif
128
129#define TCG_CT_CONST_ZERO 0x100
130#define TCG_CT_CONST_S12 0x200

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