translate.c (ff4c711b8d01608c4589cead0e2f650588d4b804) translate.c (5e3b17bbe9cc49c67d68f4a676113361944c8709)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 1655 unchanged lines hidden (view full) ---

1664
1665 gen(tcg_env);
1666
1667 gen_op_store_QT0_fpr(QFPREG(rd));
1668 gen_update_fprs_dirty(dc, QFPREG(rd));
1669}
1670#endif
1671
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 1655 unchanged lines hidden (view full) ---

1664
1665 gen(tcg_env);
1666
1667 gen_op_store_QT0_fpr(QFPREG(rd));
1668 gen_update_fprs_dirty(dc, QFPREG(rd));
1669}
1670#endif
1671
1672static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1673 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1674{
1675 TCGv_i64 src1, src2;
1676
1677 src1 = gen_load_fpr_D(dc, rs1);
1678 src2 = gen_load_fpr_D(dc, rs2);
1679
1680 gen(tcg_env, src1, src2);
1681 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
1682
1683 gen_op_store_QT0_fpr(QFPREG(rd));
1684 gen_update_fprs_dirty(dc, QFPREG(rd));
1685}
1686
1687#ifdef TARGET_SPARC64
1688static void gen_fop_DF(DisasContext *dc, int rd, int rs,
1689 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1690{
1691 TCGv_i64 dst;
1692 TCGv_i32 src;
1693
1694 src = gen_load_fpr_F(dc, rs);

--- 3282 unchanged lines hidden (view full) ---

4977 return advance_pc(dc);
4978}
4979
4980TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq)
4981TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq)
4982TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq)
4983TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq)
4984
1672#ifdef TARGET_SPARC64
1673static void gen_fop_DF(DisasContext *dc, int rd, int rs,
1674 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1675{
1676 TCGv_i64 dst;
1677 TCGv_i32 src;
1678
1679 src = gen_load_fpr_F(dc, rs);

--- 3282 unchanged lines hidden (view full) ---

4962 return advance_pc(dc);
4963}
4964
4965TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq)
4966TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq)
4967TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq)
4968TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq)
4969
4970static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
4971{
4972 TCGv_i64 src1, src2;
4973
4974 if (gen_trap_ifnofpu(dc)) {
4975 return true;
4976 }
4977 if (gen_trap_float128(dc)) {
4978 return true;
4979 }
4980
4981 gen_op_clear_ieee_excp_and_FTT();
4982 src1 = gen_load_fpr_D(dc, a->rs1);
4983 src2 = gen_load_fpr_D(dc, a->rs2);
4984 gen_helper_fdmulq(tcg_env, src1, src2);
4985 gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
4986 gen_op_store_QT0_fpr(QFPREG(a->rd));
4987 gen_update_fprs_dirty(dc, QFPREG(a->rd));
4988 return advance_pc(dc);
4989}
4990
4985#define CHECK_IU_FEATURE(dc, FEATURE) \
4986 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
4987 goto illegal_insn;
4988#define CHECK_FPU_FEATURE(dc, FEATURE) \
4989 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
4990 goto nfpu_insn;
4991
4992/* before an instruction, dc->pc must be static */

--- 50 unchanged lines hidden (view full) ---

5043 case 0x46: /* fsubd */
5044 case 0x4a: /* fmuld */
5045 case 0x4e: /* fdivd */
5046 case 0x43: /* faddq */
5047 case 0x47: /* fsubq */
5048 case 0x4b: /* fmulq */
5049 case 0x4f: /* fdivq */
5050 case 0x69: /* fsmuld */
4991#define CHECK_IU_FEATURE(dc, FEATURE) \
4992 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
4993 goto illegal_insn;
4994#define CHECK_FPU_FEATURE(dc, FEATURE) \
4995 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
4996 goto nfpu_insn;
4997
4998/* before an instruction, dc->pc must be static */

--- 50 unchanged lines hidden (view full) ---

5049 case 0x46: /* fsubd */
5050 case 0x4a: /* fmuld */
5051 case 0x4e: /* fdivd */
5052 case 0x43: /* faddq */
5053 case 0x47: /* fsubq */
5054 case 0x4b: /* fmulq */
5055 case 0x4f: /* fdivq */
5056 case 0x69: /* fsmuld */
5051 g_assert_not_reached(); /* in decodetree */
5052 case 0x6e: /* fdmulq */
5057 case 0x6e: /* fdmulq */
5053 CHECK_FPU_FEATURE(dc, FLOAT128);
5054 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
5055 break;
5058 g_assert_not_reached(); /* in decodetree */
5056 case 0xc6: /* fdtos */
5057 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
5058 break;
5059 case 0xc7: /* fqtos */
5060 CHECK_FPU_FEATURE(dc, FLOAT128);
5061 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
5062 break;
5063 case 0xc8: /* fitod */

--- 688 unchanged lines hidden --- 		5059 case 0xc6: /* fdtos */
5060 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
5061 break;
5062 case 0xc7: /* fqtos */
5063 CHECK_FPU_FEATURE(dc, FLOAT128);
5064 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
5065 break;
5066 case 0xc8: /* fitod */

--- 688 unchanged lines hidden ---