translate.c (f7ec8155f5714df29af2596b2468dd597c137256) translate.c (40f9ad219bb991b50318836612b7331f35c7bb3b)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 5111 unchanged lines hidden (view full) ---

5120 func(dc, &cmp, a->rd, a->rs2);
5121 return advance_pc(dc);
5122}
5123
5124TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs)
5125TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd)
5126TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
5127
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 5111 unchanged lines hidden (view full) ---

5120 func(dc, &cmp, a->rd, a->rs2);
5121 return advance_pc(dc);
5122}
5123
5124TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs)
5125TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd)
5126TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
5127
5128static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e)
5129{
5130 TCGv_i32 src1, src2;
5131
5132 if (avail_32(dc) && a->cc != 0) {
5133 return false;
5134 }
5135 if (gen_trap_ifnofpu(dc)) {
5136 return true;
5137 }
5138
5139 gen_op_clear_ieee_excp_and_FTT();
5140 src1 = gen_load_fpr_F(dc, a->rs1);
5141 src2 = gen_load_fpr_F(dc, a->rs2);
5142 if (e) {
5143 gen_op_fcmpes(a->cc, src1, src2);
5144 } else {
5145 gen_op_fcmps(a->cc, src1, src2);
5146 }
5147 return advance_pc(dc);
5148}
5149
5150TRANS(FCMPs, ALL, do_fcmps, a, false)
5151TRANS(FCMPEs, ALL, do_fcmps, a, true)
5152
5153static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, bool e)
5154{
5155 TCGv_i64 src1, src2;
5156
5157 if (avail_32(dc) && a->cc != 0) {
5158 return false;
5159 }
5160 if (gen_trap_ifnofpu(dc)) {
5161 return true;
5162 }
5163
5164 gen_op_clear_ieee_excp_and_FTT();
5165 src1 = gen_load_fpr_D(dc, a->rs1);
5166 src2 = gen_load_fpr_D(dc, a->rs2);
5167 if (e) {
5168 gen_op_fcmped(a->cc, src1, src2);
5169 } else {
5170 gen_op_fcmpd(a->cc, src1, src2);
5171 }
5172 return advance_pc(dc);
5173}
5174
5175TRANS(FCMPd, ALL, do_fcmpd, a, false)
5176TRANS(FCMPEd, ALL, do_fcmpd, a, true)
5177
5178static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e)
5179{
5180 if (avail_32(dc) && a->cc != 0) {
5181 return false;
5182 }
5183 if (gen_trap_ifnofpu(dc)) {
5184 return true;
5185 }
5186 if (gen_trap_float128(dc)) {
5187 return true;
5188 }
5189
5190 gen_op_clear_ieee_excp_and_FTT();
5191 gen_op_load_fpr_QT0(QFPREG(a->rs1));
5192 gen_op_load_fpr_QT1(QFPREG(a->rs2));
5193 if (e) {
5194 gen_op_fcmpeq(a->cc);
5195 } else {
5196 gen_op_fcmpq(a->cc);
5197 }
5198 return advance_pc(dc);
5199}
5200
5201TRANS(FCMPq, ALL, do_fcmpq, a, false)
5202TRANS(FCMPEq, ALL, do_fcmpq, a, true)
5203
5128#define CHECK_IU_FEATURE(dc, FEATURE) \
5129 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
5130 goto illegal_insn;
5131#define CHECK_FPU_FEATURE(dc, FEATURE) \
5132 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
5133 goto nfpu_insn;
5134
5135/* before an instruction, dc->pc must be static */
5136static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
5137{
5204#define CHECK_IU_FEATURE(dc, FEATURE) \
5205 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
5206 goto illegal_insn;
5207#define CHECK_FPU_FEATURE(dc, FEATURE) \
5208 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
5209 goto nfpu_insn;
5210
5211/* before an instruction, dc->pc must be static */
5212static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
5213{
5138 unsigned int opc, rs1, rs2, rd;
5139 TCGv cpu_src1 __attribute__((unused));
5140 TCGv_i32 cpu_src1_32, cpu_src2_32;
5141 TCGv_i64 cpu_src1_64, cpu_src2_64;
5142 TCGv_i32 cpu_dst_32 __attribute__((unused));
5143 TCGv_i64 cpu_dst_64 __attribute__((unused));
5214 unsigned int opc = GET_FIELD(insn, 0, 1);
5144
5215
5145 opc = GET_FIELD(insn, 0, 1);
5146 rd = GET_FIELD(insn, 2, 6);
5147
5148 switch (opc) {
5149 case 0:
5150 goto illegal_insn; /* in decodetree */
5151 case 1:
5152 g_assert_not_reached(); /* in decodetree */
5153 case 2: /* FPU & Logical Operations */
5154 {
5155 unsigned int xop = GET_FIELD(insn, 7, 12);
5216 switch (opc) {
5217 case 0:
5218 goto illegal_insn; /* in decodetree */
5219 case 1:
5220 g_assert_not_reached(); /* in decodetree */
5221 case 2: /* FPU & Logical Operations */
5222 {
5223 unsigned int xop = GET_FIELD(insn, 7, 12);
5156 TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
5157
5158 if (xop == 0x34) { /* FPU Operations */
5159 goto illegal_insn; /* in decodetree */
5160 } else if (xop == 0x35) { /* FPU Operations */
5224
5225 if (xop == 0x34) { /* FPU Operations */
5226 goto illegal_insn; /* in decodetree */
5227 } else if (xop == 0x35) { /* FPU Operations */
5161 if (gen_trap_ifnofpu(dc)) {
5162 goto jmp_insn;
5163 }
5164 gen_op_clear_ieee_excp_and_FTT();
5165 rs1 = GET_FIELD(insn, 13, 17);
5166 rs2 = GET_FIELD(insn, 27, 31);
5167 xop = GET_FIELD(insn, 18, 26);
5168
5169 switch (xop) {
5170 case 0x51: /* fcmps, V9 %fcc */
5171 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5172 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
5173 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
5174 break;
5175 case 0x52: /* fcmpd, V9 %fcc */
5176 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5177 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
5178 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
5179 break;
5180 case 0x53: /* fcmpq, V9 %fcc */
5181 CHECK_FPU_FEATURE(dc, FLOAT128);
5182 gen_op_load_fpr_QT0(QFPREG(rs1));
5183 gen_op_load_fpr_QT1(QFPREG(rs2));
5184 gen_op_fcmpq(rd & 3);
5185 break;
5186 case 0x55: /* fcmpes, V9 %fcc */
5187 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5188 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
5189 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
5190 break;
5191 case 0x56: /* fcmped, V9 %fcc */
5192 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5193 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
5194 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
5195 break;
5196 case 0x57: /* fcmpeq, V9 %fcc */
5197 CHECK_FPU_FEATURE(dc, FLOAT128);
5198 gen_op_load_fpr_QT0(QFPREG(rs1));
5199 gen_op_load_fpr_QT1(QFPREG(rs2));
5200 gen_op_fcmpeq(rd & 3);
5201 break;
5202 default:
5203 goto illegal_insn;
5204 }
5228 goto illegal_insn; /* in decodetree */
5205 } else if (xop == 0x36) {
5206#ifdef TARGET_SPARC64
5207 /* VIS */
5229 } else if (xop == 0x36) {
5230#ifdef TARGET_SPARC64
5231 /* VIS */
5232 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
5233 TCGv_i32 cpu_dst_32;
5234 TCGv cpu_dst = tcg_temp_new();
5208 int opf = GET_FIELD_SP(insn, 5, 13);
5235 int opf = GET_FIELD_SP(insn, 5, 13);
5209 rs1 = GET_FIELD(insn, 13, 17);
5210 rs2 = GET_FIELD(insn, 27, 31);
5236 int rs1 = GET_FIELD(insn, 13, 17);
5237 int rs2 = GET_FIELD(insn, 27, 31);
5238 int rd = GET_FIELD(insn, 2, 6);
5239
5211 if (gen_trap_ifnofpu(dc)) {
5212 goto jmp_insn;
5213 }
5214
5215 switch (opf) {
5216 case 0x000: /* VIS I edge8cc */
5217 case 0x001: /* VIS II edge8n */
5218 case 0x002: /* VIS I edge8lcc */

--- 168 unchanged lines hidden (view full) ---

5387 goto illegal_insn; /* in decodetree */
5388 }
5389 }
5390 break;
5391 case 3: /* load/store instructions */
5392 goto illegal_insn; /* in decodetree */
5393 }
5394 advance_pc(dc);
5240 if (gen_trap_ifnofpu(dc)) {
5241 goto jmp_insn;
5242 }
5243
5244 switch (opf) {
5245 case 0x000: /* VIS I edge8cc */
5246 case 0x001: /* VIS II edge8n */
5247 case 0x002: /* VIS I edge8lcc */

--- 168 unchanged lines hidden (view full) ---

5416 goto illegal_insn; /* in decodetree */
5417 }
5418 }
5419 break;
5420 case 3: /* load/store instructions */
5421 goto illegal_insn; /* in decodetree */
5422 }
5423 advance_pc(dc);
5424#ifdef TARGET_SPARC64
5395 jmp_insn:
5425 jmp_insn:
5426#endif
5396 return;
5397 illegal_insn:
5398 gen_exception(dc, TT_ILL_INSN);
5399 return;
5427 return;
5428 illegal_insn:
5429 gen_exception(dc, TT_ILL_INSN);
5430 return;
5431#ifdef TARGET_SPARC64
5400 nfpu_insn:
5401 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
5402 return;
5432 nfpu_insn:
5433 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
5434 return;
5435#endif
5403}
5404
5405static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5406{
5407 DisasContext *dc = container_of(dcbase, DisasContext, base);
5408 CPUSPARCState *env = cpu_env(cs);
5409 int bound;
5410

--- 272 unchanged lines hidden --- 		5436}
5437
5438static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5439{
5440 DisasContext *dc = container_of(dcbase, DisasContext, base);
5441 CPUSPARCState *env = cpu_env(cs);
5442 int bound;
5443

--- 272 unchanged lines hidden ---