translate.c (f2cfa1229e539ee1bb1822912075cf25538ad6b9) translate.c (14776ab5a12972ea439c7fb2203a4c15a09094b4)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

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2014
2015 gen(cpu_env, src);
2016
2017 gen_op_store_QT0_fpr(QFPREG(rd));
2018 gen_update_fprs_dirty(dc, QFPREG(rd));
2019}
2020
2021static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 2005 unchanged lines hidden (view full) ---

2014
2015 gen(cpu_env, src);
2016
2017 gen_op_store_QT0_fpr(QFPREG(rd));
2018 gen_update_fprs_dirty(dc, QFPREG(rd));
2019}
2020
2021static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
2022 TCGv addr, int mmu_idx, TCGMemOp memop)
2022 TCGv addr, int mmu_idx, MemOp memop)
2023{
2024 gen_address_mask(dc, addr);
2025 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
2026}
2027
2028static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2029{
2030 TCGv m1 = tcg_const_tl(0xff);

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2045 GET_ASI_BCOPY,
2046 GET_ASI_BFILL,
2047} ASIType;
2048
2049typedef struct {
2050 ASIType type;
2051 int asi;
2052 int mem_idx;
2023{
2024 gen_address_mask(dc, addr);
2025 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
2026}
2027
2028static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2029{
2030 TCGv m1 = tcg_const_tl(0xff);

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2045 GET_ASI_BCOPY,
2046 GET_ASI_BFILL,
2047} ASIType;
2048
2049typedef struct {
2050 ASIType type;
2051 int asi;
2052 int mem_idx;
2053 TCGMemOp memop;
2053 MemOp memop;
2054} DisasASI;
2055
2054} DisasASI;
2055
2056static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
2056static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
2057{
2058 int asi = GET_FIELD(insn, 19, 26);
2059 ASIType type = GET_ASI_HELPER;
2060 int mem_idx = dc->mem_idx;
2061
2062#ifndef TARGET_SPARC64
2063 /* Before v9, all asis are immediate and privileged. */
2064 if (IS_IMM) {

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2262 }
2263 }
2264#endif
2265
2266 return (DisasASI){ type, asi, mem_idx, memop };
2267}
2268
2269static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
2057{
2058 int asi = GET_FIELD(insn, 19, 26);
2059 ASIType type = GET_ASI_HELPER;
2060 int mem_idx = dc->mem_idx;
2061
2062#ifndef TARGET_SPARC64
2063 /* Before v9, all asis are immediate and privileged. */
2064 if (IS_IMM) {

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2262 }
2263 }
2264#endif
2265
2266 return (DisasASI){ type, asi, mem_idx, memop };
2267}
2268
2269static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
2270 int insn, TCGMemOp memop)
2270 int insn, MemOp memop)
2271{
2272 DisasASI da = get_asi(dc, insn, memop);
2273
2274 switch (da.type) {
2275 case GET_ASI_EXCP:
2276 break;
2277 case GET_ASI_DTWINX: /* Reserved for ldda. */
2278 gen_exception(dc, TT_ILL_INSN);

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2300 tcg_temp_free_i32(r_mop);
2301 tcg_temp_free_i32(r_asi);
2302 }
2303 break;
2304 }
2305}
2306
2307static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
2271{
2272 DisasASI da = get_asi(dc, insn, memop);
2273
2274 switch (da.type) {
2275 case GET_ASI_EXCP:
2276 break;
2277 case GET_ASI_DTWINX: /* Reserved for ldda. */
2278 gen_exception(dc, TT_ILL_INSN);

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2300 tcg_temp_free_i32(r_mop);
2301 tcg_temp_free_i32(r_asi);
2302 }
2303 break;
2304 }
2305}
2306
2307static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
2308 int insn, TCGMemOp memop)
2308 int insn, MemOp memop)
2309{
2310 DisasASI da = get_asi(dc, insn, memop);
2311
2312 switch (da.type) {
2313 case GET_ASI_EXCP:
2314 break;
2315 case GET_ASI_DTWINX: /* Reserved for stda. */
2316#ifndef TARGET_SPARC64

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2506 default:
2507 g_assert_not_reached();
2508 }
2509 break;
2510
2511 case GET_ASI_BLOCK:
2512 /* Valid for lddfa on aligned registers only. */
2513 if (size == 8 && (rd & 7) == 0) {
2309{
2310 DisasASI da = get_asi(dc, insn, memop);
2311
2312 switch (da.type) {
2313 case GET_ASI_EXCP:
2314 break;
2315 case GET_ASI_DTWINX: /* Reserved for stda. */
2316#ifndef TARGET_SPARC64

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2506 default:
2507 g_assert_not_reached();
2508 }
2509 break;
2510
2511 case GET_ASI_BLOCK:
2512 /* Valid for lddfa on aligned registers only. */
2513 if (size == 8 && (rd & 7) == 0) {
2514 TCGMemOp memop;
2514 MemOp memop;
2515 TCGv eight;
2516 int i;
2517
2518 gen_address_mask(dc, addr);
2519
2520 /* The first operation checks required alignment. */
2521 memop = da.memop | MO_ALIGN_64;
2522 eight = tcg_const_tl(8);

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2620 default:
2621 g_assert_not_reached();
2622 }
2623 break;
2624
2625 case GET_ASI_BLOCK:
2626 /* Valid for stdfa on aligned registers only. */
2627 if (size == 8 && (rd & 7) == 0) {
2515 TCGv eight;
2516 int i;
2517
2518 gen_address_mask(dc, addr);
2519
2520 /* The first operation checks required alignment. */
2521 memop = da.memop | MO_ALIGN_64;
2522 eight = tcg_const_tl(8);

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2620 default:
2621 g_assert_not_reached();
2622 }
2623 break;
2624
2625 case GET_ASI_BLOCK:
2626 /* Valid for stdfa on aligned registers only. */
2627 if (size == 8 && (rd & 7) == 0) {
2628 TCGMemOp memop;
2628 MemOp memop;
2629 TCGv eight;
2630 int i;
2631
2632 gen_address_mask(dc, addr);
2633
2634 /* The first operation checks required alignment. */
2635 memop = da.memop | MO_ALIGN_64;
2636 eight = tcg_const_tl(8);

--- 3425 unchanged lines hidden --- 		2629 TCGv eight;
2630 int i;
2631
2632 gen_address_mask(dc, addr);
2633
2634 /* The first operation checks required alignment. */
2635 memop = da.memop | MO_ALIGN_64;
2636 eight = tcg_const_tl(8);

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