| translate.c (be8998e046c2a7e434494b75cf468ffd9d536025) | translate.c (d3ef26afde77fbdedd5b30282134ff99d0fe5cc5) |
|---|---|
| 1/* 2 SPARC translation 3 4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> 5 Copyright (C) 2003-2005 Fabrice Bellard 6 7 This library is free software; you can redistribute it and/or 8 modify it under the terms of the GNU Lesser General Public --- 4642 unchanged lines hidden (view full) --- 4651 gen_store_fpr_D(dc, a->rd, dst); 4652 return advance_pc(dc); 4653} 4654 4655TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au) 4656TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al) 4657TRANS(FMULD8SUx16, VIS1, do_dff, a, gen_op_fmuld8sux16) 4658TRANS(FMULD8ULx16, VIS1, do_dff, a, gen_op_fmuld8ulx16) | 1/* 2 SPARC translation 3 4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> 5 Copyright (C) 2003-2005 Fabrice Bellard 6 7 This library is free software; you can redistribute it and/or 8 modify it under the terms of the GNU Lesser General Public --- 4642 unchanged lines hidden (view full) --- 4651 gen_store_fpr_D(dc, a->rd, dst); 4652 return advance_pc(dc); 4653} 4654 4655TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au) 4656TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al) 4657TRANS(FMULD8SUx16, VIS1, do_dff, a, gen_op_fmuld8sux16) 4658TRANS(FMULD8ULx16, VIS1, do_dff, a, gen_op_fmuld8ulx16) |
| 4659TRANS(FPMERGE, VIS1, do_dff, a, gen_helper_fpmerge) |
|
| 4659 4660static bool do_dfd(DisasContext *dc, arg_r_r_r *a, 4661 void (*func)(TCGv_i64, TCGv_i32, TCGv_i64)) 4662{ 4663 TCGv_i64 dst, src2; 4664 TCGv_i32 src1; 4665 4666 if (gen_trap_ifnofpu(dc)) { --- 24 unchanged lines hidden (view full) --- 4691 src2 = gen_load_fpr_D(dc, a->rs2); 4692 func(dst, src1, src2); 4693 gen_store_fpr_D(dc, a->rd, dst); 4694 return advance_pc(dc); 4695} 4696 4697TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) 4698TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) | 4660 4661static bool do_dfd(DisasContext *dc, arg_r_r_r *a, 4662 void (*func)(TCGv_i64, TCGv_i32, TCGv_i64)) 4663{ 4664 TCGv_i64 dst, src2; 4665 TCGv_i32 src1; 4666 4667 if (gen_trap_ifnofpu(dc)) { --- 24 unchanged lines hidden (view full) --- 4692 src2 = gen_load_fpr_D(dc, a->rs2); 4693 func(dst, src1, src2); 4694 gen_store_fpr_D(dc, a->rd, dst); 4695 return advance_pc(dc); 4696} 4697 4698TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) 4699TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) |
| 4699TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) | |
| 4700 4701TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) 4702TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) 4703TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64) 4704TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64) 4705TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64) 4706TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64) 4707TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64) --- 568 unchanged lines hidden --- | 4700 4701TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) 4702TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) 4703TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64) 4704TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64) 4705TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64) 4706TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64) 4707TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64) --- 568 unchanged lines hidden --- |