translate.c (bb97f2f5d77227cc6b5edeed637218e7dd214816) translate.c (cd6269f7c966f8c8119abc0318dd6b60a8376989)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

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79static TCGv cpu_y;
80static TCGv cpu_tbr;
81static TCGv cpu_cond;
82#ifdef TARGET_SPARC64
83static TCGv_i32 cpu_xcc, cpu_fprs;
84static TCGv cpu_gsr;
85static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
86static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

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79static TCGv cpu_y;
80static TCGv cpu_tbr;
81static TCGv cpu_cond;
82#ifdef TARGET_SPARC64
83static TCGv_i32 cpu_xcc, cpu_fprs;
84static TCGv cpu_gsr;
85static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
86static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
87# define cpu_wim ({ qemu_build_not_reached(); (TCGv)NULL; })
88#else
87#else
89static TCGv cpu_wim;
90# define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; })
91# define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; })
92# define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; })
93# define cpu_hstick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
94# define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; })
95# define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; })
96# define cpu_ssr ({ qemu_build_not_reached(); (TCGv)NULL; })
97# define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
98# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
99# define cpu_ver ({ qemu_build_not_reached(); (TCGv)NULL; })
100#endif
101/* Floating point registers */
102static TCGv_i64 cpu_fpr[TARGET_DPREGS];
103
104#define env_field_offsetof(X) offsetof(CPUSPARCState, X)
105#ifdef TARGET_SPARC64
88# define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; })
89# define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; })
90# define cpu_hintp ({ qemu_build_not_reached(); (TCGv)NULL; })
91# define cpu_hstick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
92# define cpu_htba ({ qemu_build_not_reached(); (TCGv)NULL; })
93# define cpu_hver ({ qemu_build_not_reached(); (TCGv)NULL; })
94# define cpu_ssr ({ qemu_build_not_reached(); (TCGv)NULL; })
95# define cpu_stick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
96# define cpu_tick_cmpr ({ qemu_build_not_reached(); (TCGv)NULL; })
97# define cpu_ver ({ qemu_build_not_reached(); (TCGv)NULL; })
98#endif
99/* Floating point registers */
100static TCGv_i64 cpu_fpr[TARGET_DPREGS];
101
102#define env_field_offsetof(X) offsetof(CPUSPARCState, X)
103#ifdef TARGET_SPARC64
104# define env32_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
106# define env64_field_offsetof(X) env_field_offsetof(X)
107#else
105# define env64_field_offsetof(X) env_field_offsetof(X)
106#else
107# define env32_field_offsetof(X) env_field_offsetof(X)
108# define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
109#endif
110
111typedef struct DisasDelayException {
112 struct DisasDelayException *next;
113 TCGLabel *lab;
114 TCGv_i32 excp;
115 /* Saved state at parent insn. */

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3409 return cpu_hstick_cmpr;
3410}
3411
3412TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd,
3413 do_rdhstick_cmpr)
3414
3415static TCGv do_rdwim(DisasContext *dc, TCGv dst)
3416{
108# define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
109#endif
110
111typedef struct DisasDelayException {
112 struct DisasDelayException *next;
113 TCGLabel *lab;
114 TCGv_i32 excp;
115 /* Saved state at parent insn. */

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3409 return cpu_hstick_cmpr;
3410}
3411
3412TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd,
3413 do_rdhstick_cmpr)
3414
3415static TCGv do_rdwim(DisasContext *dc, TCGv dst)
3416{
3417 return cpu_wim;
3417 tcg_gen_ld_tl(dst, tcg_env, env32_field_offsetof(wim));
3418 return dst;
3418}
3419
3420TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim)
3421
3422static TCGv do_rdtpc(DisasContext *dc, TCGv dst)
3423{
3424#ifdef TARGET_SPARC64
3425 TCGv_ptr r_tsptr = tcg_temp_new_ptr();

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3762 dc->base.is_jmp = DISAS_EXIT;
3763}
3764
3765TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
3766
3767static void do_wrwim(DisasContext *dc, TCGv src)
3768{
3769 target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);
3419}
3420
3421TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim)
3422
3423static TCGv do_rdtpc(DisasContext *dc, TCGv dst)
3424{
3425#ifdef TARGET_SPARC64
3426 TCGv_ptr r_tsptr = tcg_temp_new_ptr();

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3763 dc->base.is_jmp = DISAS_EXIT;
3764}
3765
3766TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
3767
3768static void do_wrwim(DisasContext *dc, TCGv src)
3769{
3770 target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);
3770 tcg_gen_andi_tl(cpu_wim, src, mask);
3771 TCGv tmp = tcg_temp_new();
3772
3773 tcg_gen_andi_tl(tmp, src, mask);
3774 tcg_gen_st_tl(tmp, tcg_env, env32_field_offsetof(wim));
3771}
3772
3773TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim)
3774
3775static void do_wrtpc(DisasContext *dc, TCGv src)
3776{
3777#ifdef TARGET_SPARC64
3778 TCGv_ptr r_tsptr = tcg_temp_new_ptr();

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5934 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5935 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5936 };
5937
5938 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
5939#ifdef TARGET_SPARC64
5940 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
5941 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
3775}
3776
3777TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim)
3778
3779static void do_wrtpc(DisasContext *dc, TCGv src)
3780{
3781#ifdef TARGET_SPARC64
3782 TCGv_ptr r_tsptr = tcg_temp_new_ptr();

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5938 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5939 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5940 };
5941
5942 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
5943#ifdef TARGET_SPARC64
5944 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
5945 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
5942#else
5943 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5944#endif
5945 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5946 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5947 };
5948
5949 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5950#ifdef TARGET_SPARC64
5951 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },

--- 78 unchanged lines hidden --- 		5946#endif
5947 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5948 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5949 };
5950
5951 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5952#ifdef TARGET_SPARC64
5953 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },

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