translate.c (68524e83f8fbe23dca37dc5b847fb558d75c8fab) translate.c (b597eedcce0de84ff573a6be2cd6a89c7fa0fd8e)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 91 unchanged lines hidden (view full) ---

100#define JUMP_PC 2
101/* Dynamic PC, may lookup next TB. */
102#define DYNAMIC_PC_LOOKUP 3
103
104#define DISAS_EXIT DISAS_TARGET_0
105
106/* global register indexes */
107static TCGv_ptr cpu_regwptr;
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 91 unchanged lines hidden (view full) ---

100#define JUMP_PC 2
101/* Dynamic PC, may lookup next TB. */
102#define DYNAMIC_PC_LOOKUP 3
103
104#define DISAS_EXIT DISAS_TARGET_0
105
106/* global register indexes */
107static TCGv_ptr cpu_regwptr;
108static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
109static TCGv_i32 cpu_cc_op;
110static TCGv cpu_fsr, cpu_pc, cpu_npc;
111static TCGv cpu_regs[32];
112static TCGv cpu_y;
113static TCGv cpu_tbr;
114static TCGv cpu_cond;
115static TCGv cpu_cc_N;
116static TCGv cpu_cc_V;
117static TCGv cpu_icc_Z;

--- 49 unchanged lines hidden (view full) ---

167 bool address_mask_32bit;
168#ifndef CONFIG_USER_ONLY
169 bool supervisor;
170#ifdef TARGET_SPARC64
171 bool hypervisor;
172#endif
173#endif
174
108static TCGv cpu_fsr, cpu_pc, cpu_npc;
109static TCGv cpu_regs[32];
110static TCGv cpu_y;
111static TCGv cpu_tbr;
112static TCGv cpu_cond;
113static TCGv cpu_cc_N;
114static TCGv cpu_cc_V;
115static TCGv cpu_icc_Z;

--- 49 unchanged lines hidden (view full) ---

165 bool address_mask_32bit;
166#ifndef CONFIG_USER_ONLY
167 bool supervisor;
168#ifdef TARGET_SPARC64
169 bool hypervisor;
170#endif
171#endif
172
175 uint32_t cc_op; /* current CC operation */
176 sparc_def_t *def;
177#ifdef TARGET_SPARC64
178 int fprs_dirty;
179 int asi;
180#endif
181 DisasDelayException *delay_excp_list;
182} DisasContext;
183

--- 773 unchanged lines hidden (view full) ---

957 default:
958 g_assert_not_reached();
959 }
960 } else {
961 tcg_gen_movi_tl(cpu_npc, dc->npc);
962 }
963}
964
173 sparc_def_t *def;
174#ifdef TARGET_SPARC64
175 int fprs_dirty;
176 int asi;
177#endif
178 DisasDelayException *delay_excp_list;
179} DisasContext;
180

--- 773 unchanged lines hidden (view full) ---

954 default:
955 g_assert_not_reached();
956 }
957 } else {
958 tcg_gen_movi_tl(cpu_npc, dc->npc);
959 }
960}
961
965static void update_psr(DisasContext *dc)
966{
967 if (dc->cc_op != CC_OP_FLAGS) {
968 dc->cc_op = CC_OP_FLAGS;
969 gen_helper_compute_psr(tcg_env);
970 }
971}
972
973static void save_state(DisasContext *dc)
974{
975 tcg_gen_movi_tl(cpu_pc, dc->pc);
976 save_npc(dc);
977}
978
979static void gen_exception(DisasContext *dc, int which)
980{

--- 62 unchanged lines hidden (view full) ---

1043{
1044 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1045 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1046}
1047
1048static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
1049 DisasContext *dc)
1050{
962static void save_state(DisasContext *dc)
963{
964 tcg_gen_movi_tl(cpu_pc, dc->pc);
965 save_npc(dc);
966}
967
968static void gen_exception(DisasContext *dc, int which)
969{

--- 62 unchanged lines hidden (view full) ---

1032{
1033 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1034 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1035}
1036
1037static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
1038 DisasContext *dc)
1039{
1051 TCGv t1, t2;
1040 TCGv t1;
1052
1053 cmp->is_bool = false;
1041
1042 cmp->is_bool = false;
1054
1055 switch (dc->cc_op) {
1056 default:
1057 gen_helper_compute_psr(tcg_env);
1058 dc->cc_op = CC_OP_FLAGS;
1059 break;
1060
1061 case CC_OP_FLAGS:
1062 break;
1063 }
1064
1065 cmp->c1 = t1 = tcg_temp_new();
1066 cmp->c2 = tcg_constant_tl(0);
1067
1068 switch (cond & 7) {
1069 case 0x0: /* never */
1070 cmp->cond = TCG_COND_NEVER;
1071 cmp->c1 = cmp->c2;
1072 break;

--- 1661 unchanged lines hidden (view full) ---

2734
2735 return tcg_constant_tl(val);
2736}
2737
2738TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
2739
2740static TCGv do_rdccr(DisasContext *dc, TCGv dst)
2741{
1043 cmp->c1 = t1 = tcg_temp_new();
1044 cmp->c2 = tcg_constant_tl(0);
1045
1046 switch (cond & 7) {
1047 case 0x0: /* never */
1048 cmp->cond = TCG_COND_NEVER;
1049 cmp->c1 = cmp->c2;
1050 break;

--- 1661 unchanged lines hidden (view full) ---

2712
2713 return tcg_constant_tl(val);
2714}
2715
2716TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
2717
2718static TCGv do_rdccr(DisasContext *dc, TCGv dst)
2719{
2742 update_psr(dc);
2743 gen_helper_rdccr(dst, tcg_env);
2744 return dst;
2745}
2746
2747TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr)
2748
2749static TCGv do_rdasi(DisasContext *dc, TCGv dst)
2750{

--- 96 unchanged lines hidden (view full) ---

2847{
2848 return tcg_constant_tl(1);
2849}
2850
2851TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status)
2852
2853static TCGv do_rdpsr(DisasContext *dc, TCGv dst)
2854{
2720 gen_helper_rdccr(dst, tcg_env);
2721 return dst;
2722}
2723
2724TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr)
2725
2726static TCGv do_rdasi(DisasContext *dc, TCGv dst)
2727{

--- 96 unchanged lines hidden (view full) ---

2824{
2825 return tcg_constant_tl(1);
2826}
2827
2828TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status)
2829
2830static TCGv do_rdpsr(DisasContext *dc, TCGv dst)
2831{
2855 update_psr(dc);
2856 gen_helper_rdpsr(dst, tcg_env);
2857 return dst;
2858}
2859
2860TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr)
2861
2862static TCGv do_rdhpstate(DisasContext *dc, TCGv dst)
2863{

--- 388 unchanged lines hidden (view full) ---

3252 gen_helper_power_down(tcg_env);
3253}
3254
3255TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown)
3256
3257static void do_wrpsr(DisasContext *dc, TCGv src)
3258{
3259 gen_helper_wrpsr(tcg_env, src);
2832 gen_helper_rdpsr(dst, tcg_env);
2833 return dst;
2834}
2835
2836TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr)
2837
2838static TCGv do_rdhpstate(DisasContext *dc, TCGv dst)
2839{

--- 388 unchanged lines hidden (view full) ---

3228 gen_helper_power_down(tcg_env);
3229}
3230
3231TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown)
3232
3233static void do_wrpsr(DisasContext *dc, TCGv src)
3234{
3235 gen_helper_wrpsr(tcg_env, src);
3260 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3261 dc->cc_op = CC_OP_FLAGS;
3262 dc->base.is_jmp = DISAS_EXIT;
3263}
3264
3265TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
3266
3267static void do_wrwim(DisasContext *dc, TCGv src)
3268{
3269 target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);

--- 247 unchanged lines hidden (view full) ---

3517
3518/*
3519 * TODO: Need a feature bit for sparcv8.
3520 * In the meantime, treat all 32-bit cpus like sparcv7.
3521 */
3522TRANS(NOP_v7, 32, trans_NOP, a)
3523TRANS(NOP_v9, 64, trans_NOP, a)
3524
3236 dc->base.is_jmp = DISAS_EXIT;
3237}
3238
3239TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
3240
3241static void do_wrwim(DisasContext *dc, TCGv src)
3242{
3243 target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows);

--- 247 unchanged lines hidden (view full) ---

3491
3492/*
3493 * TODO: Need a feature bit for sparcv8.
3494 * In the meantime, treat all 32-bit cpus like sparcv7.
3495 */
3496TRANS(NOP_v7, 32, trans_NOP, a)
3497TRANS(NOP_v9, 64, trans_NOP, a)
3498
3525static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
3499static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a,
3526 void (*func)(TCGv, TCGv, TCGv),
3527 void (*funci)(TCGv, TCGv, target_long),
3528 bool logic_cc)
3529{
3530 TCGv dst, src1;
3531
3532 /* For simplicity, we under-decoded the rs2 form. */
3533 if (!a->imm && a->rs2_or_imm & ~0x1f) {
3534 return false;
3535 }
3536
3537 if (logic_cc) {
3538 dst = cpu_cc_N;
3500 void (*func)(TCGv, TCGv, TCGv),
3501 void (*funci)(TCGv, TCGv, target_long),
3502 bool logic_cc)
3503{
3504 TCGv dst, src1;
3505
3506 /* For simplicity, we under-decoded the rs2 form. */
3507 if (!a->imm && a->rs2_or_imm & ~0x1f) {
3508 return false;
3509 }
3510
3511 if (logic_cc) {
3512 dst = cpu_cc_N;
3539 } else if (a->cc && cc_op > CC_OP_FLAGS) {
3540 dst = cpu_cc_dst;
3541 } else {
3542 dst = gen_dest_gpr(dc, a->rd);
3543 }
3544 src1 = gen_load_gpr(dc, a->rs1);
3545
3546 if (a->imm || a->rs2_or_imm == 0) {
3547 if (funci) {
3548 funci(dst, src1, a->rs2_or_imm);

--- 10 unchanged lines hidden (view full) ---

3559 tcg_gen_movi_tl(cpu_icc_C, 0);
3560 }
3561 tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
3562 tcg_gen_movi_tl(cpu_cc_C, 0);
3563 tcg_gen_movi_tl(cpu_cc_V, 0);
3564 }
3565
3566 gen_store_gpr(dc, a->rd, dst);
3513 } else {
3514 dst = gen_dest_gpr(dc, a->rd);
3515 }
3516 src1 = gen_load_gpr(dc, a->rs1);
3517
3518 if (a->imm || a->rs2_or_imm == 0) {
3519 if (funci) {
3520 funci(dst, src1, a->rs2_or_imm);

--- 10 unchanged lines hidden (view full) ---

3531 tcg_gen_movi_tl(cpu_icc_C, 0);
3532 }
3533 tcg_gen_mov_tl(cpu_cc_Z, cpu_cc_N);
3534 tcg_gen_movi_tl(cpu_cc_C, 0);
3535 tcg_gen_movi_tl(cpu_cc_V, 0);
3536 }
3537
3538 gen_store_gpr(dc, a->rd, dst);
3567
3568 if (a->cc) {
3569 tcg_gen_movi_i32(cpu_cc_op, cc_op);
3570 dc->cc_op = cc_op;
3571 }
3572 return advance_pc(dc);
3573}
3574
3539 return advance_pc(dc);
3540}
3541
3575static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
3542static bool do_arith(DisasContext *dc, arg_r_r_ri_cc *a,
3576 void (*func)(TCGv, TCGv, TCGv),
3577 void (*funci)(TCGv, TCGv, target_long),
3578 void (*func_cc)(TCGv, TCGv, TCGv))
3579{
3580 if (a->cc) {
3543 void (*func)(TCGv, TCGv, TCGv),
3544 void (*funci)(TCGv, TCGv, target_long),
3545 void (*func_cc)(TCGv, TCGv, TCGv))
3546{
3547 if (a->cc) {
3581 assert(cc_op >= 0);
3582 return do_arith_int(dc, a, cc_op, func_cc, NULL, false);
3548 return do_arith_int(dc, a, func_cc, NULL, false);
3583 }
3549 }
3584 return do_arith_int(dc, a, cc_op, func, funci, false);
3550 return do_arith_int(dc, a, func, funci, false);
3585}
3586
3587static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a,
3588 void (*func)(TCGv, TCGv, TCGv),
3589 void (*funci)(TCGv, TCGv, target_long))
3590{
3551}
3552
3553static bool do_logic(DisasContext *dc, arg_r_r_ri_cc *a,
3554 void (*func)(TCGv, TCGv, TCGv),
3555 void (*funci)(TCGv, TCGv, target_long))
3556{
3591 return do_arith_int(dc, a, CC_OP_FLAGS, func, funci, a->cc);
3557 return do_arith_int(dc, a, func, funci, a->cc);
3592}
3593
3558}
3559
3594TRANS(ADD, ALL, do_arith, a, CC_OP_FLAGS,
3595 tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc)
3596TRANS(SUB, ALL, do_arith, a, CC_OP_FLAGS,
3597 tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_subcc)
3560TRANS(ADD, ALL, do_arith, a, tcg_gen_add_tl, tcg_gen_addi_tl, gen_op_addcc)
3561TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_subcc)
3562TRANS(ADDC, ALL, do_arith, a, gen_op_addc, NULL, gen_op_addccc)
3563TRANS(SUBC, ALL, do_arith, a, gen_op_subc, NULL, gen_op_subccc)
3598
3564
3599TRANS(TADDcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcc)
3600TRANS(TSUBcc, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcc)
3601TRANS(TADDccTV, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_taddcctv)
3602TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_FLAGS, NULL, NULL, gen_op_tsubcctv)
3565TRANS(TADDcc, ALL, do_arith, a, NULL, NULL, gen_op_taddcc)
3566TRANS(TSUBcc, ALL, do_arith, a, NULL, NULL, gen_op_tsubcc)
3567TRANS(TADDccTV, ALL, do_arith, a, NULL, NULL, gen_op_taddcctv)
3568TRANS(TSUBccTV, ALL, do_arith, a, NULL, NULL, gen_op_tsubcctv)
3603
3604TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
3605TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
3606TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
3607TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
3608TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
3609
3569
3570TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
3571TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
3572TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
3573TRANS(ORN, ALL, do_logic, a, tcg_gen_orc_tl, NULL)
3574TRANS(XORN, ALL, do_logic, a, tcg_gen_eqv_tl, NULL)
3575
3610TRANS(MULX, 64, do_arith, a, -1, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL)
3576TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl, NULL)
3611TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
3612TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
3577TRANS(UMUL, MUL, do_logic, a, gen_op_umul, NULL)
3578TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
3579TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc)
3613
3580
3614TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL)
3615TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL)
3616TRANS(UDIV, DIV, do_arith, a, CC_OP_FLAGS, gen_op_udiv, NULL, gen_op_udivcc)
3617TRANS(SDIV, DIV, do_arith, a, CC_OP_FLAGS, gen_op_sdiv, NULL, gen_op_sdivcc)
3581TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL, NULL)
3582TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL, NULL)
3583TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc)
3584TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc)
3618
3619/* TODO: Should have feature bit -- comes in with UltraSparc T2. */
3585
3586/* TODO: Should have feature bit -- comes in with UltraSparc T2. */
3620TRANS(POPC, 64, do_arith, a, -1, gen_op_popc, NULL, NULL)
3587TRANS(POPC, 64, do_arith, a, gen_op_popc, NULL, NULL)
3621
3622static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
3623{
3624 /* OR with %g0 is the canonical alias for MOV. */
3625 if (!a->cc && a->rs1 == 0) {
3626 if (a->imm || a->rs2_or_imm == 0) {
3627 gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm));
3628 } else if (a->rs2_or_imm & ~0x1f) {
3629 /* For simplicity, we under-decoded the rs2 form. */
3630 return false;
3631 } else {
3632 gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]);
3633 }
3634 return advance_pc(dc);
3635 }
3636 return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
3637}
3638
3588
3589static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
3590{
3591 /* OR with %g0 is the canonical alias for MOV. */
3592 if (!a->cc && a->rs1 == 0) {
3593 if (a->imm || a->rs2_or_imm == 0) {
3594 gen_store_gpr(dc, a->rd, tcg_constant_tl(a->rs2_or_imm));
3595 } else if (a->rs2_or_imm & ~0x1f) {
3596 /* For simplicity, we under-decoded the rs2 form. */
3597 return false;
3598 } else {
3599 gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]);
3600 }
3601 return advance_pc(dc);
3602 }
3603 return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
3604}
3605
3639static bool trans_ADDC(DisasContext *dc, arg_r_r_ri_cc *a)
3640{
3641 update_psr(dc);
3642 return do_arith(dc, a, CC_OP_FLAGS, gen_op_addc, NULL, gen_op_addccc);
3643}
3644
3645static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a)
3646{
3647 update_psr(dc);
3648 return do_arith(dc, a, CC_OP_FLAGS, gen_op_subc, NULL, gen_op_subccc);
3649}
3650
3651static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
3652{
3653 update_psr(dc);
3654 return do_arith(dc, a, CC_OP_FLAGS, NULL, NULL, gen_op_mulscc);
3655}
3656
3657static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
3658 int width, bool cc, bool left)
3659{
3660 TCGv dst, s1, s2, lo1, lo2;
3661 uint64_t amask, tabl, tabr;
3662 int shift, imask, omask;
3663
3664 dst = gen_dest_gpr(dc, a->rd);
3665 s1 = gen_load_gpr(dc, a->rs1);
3666 s2 = gen_load_gpr(dc, a->rs2);
3667
3668 if (cc) {
3669 gen_op_subcc(cpu_cc_N, s1, s2);
3606static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
3607 int width, bool cc, bool left)
3608{
3609 TCGv dst, s1, s2, lo1, lo2;
3610 uint64_t amask, tabl, tabr;
3611 int shift, imask, omask;
3612
3613 dst = gen_dest_gpr(dc, a->rd);
3614 s1 = gen_load_gpr(dc, a->rs1);
3615 s2 = gen_load_gpr(dc, a->rs2);
3616
3617 if (cc) {
3618 gen_op_subcc(cpu_cc_N, s1, s2);
3670 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3671 dc->cc_op = CC_OP_FLAGS;
3672 }
3673
3674 /*
3675 * Theory of operation: there are two tables, left and right (not to
3676 * be confused with the left and right versions of the opcode). These
3677 * are indexed by the low 3 bits of the inputs. To make things "easy",
3678 * these tables are loaded into two constants, TABL and TABR below.
3679 * The operation index = (input & imask) << shift calculates the index

--- 1395 unchanged lines hidden (view full) ---

5075static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5076{
5077 DisasContext *dc = container_of(dcbase, DisasContext, base);
5078 CPUSPARCState *env = cpu_env(cs);
5079 int bound;
5080
5081 dc->pc = dc->base.pc_first;
5082 dc->npc = (target_ulong)dc->base.tb->cs_base;
3619 }
3620
3621 /*
3622 * Theory of operation: there are two tables, left and right (not to
3623 * be confused with the left and right versions of the opcode). These
3624 * are indexed by the low 3 bits of the inputs. To make things "easy",
3625 * these tables are loaded into two constants, TABL and TABR below.
3626 * The operation index = (input & imask) << shift calculates the index

--- 1395 unchanged lines hidden (view full) ---

5022static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5023{
5024 DisasContext *dc = container_of(dcbase, DisasContext, base);
5025 CPUSPARCState *env = cpu_env(cs);
5026 int bound;
5027
5028 dc->pc = dc->base.pc_first;
5029 dc->npc = (target_ulong)dc->base.tb->cs_base;
5083 dc->cc_op = CC_OP_DYNAMIC;
5084 dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
5085 dc->def = &env->def;
5086 dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
5087 dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
5088#ifndef CONFIG_USER_ONLY
5089 dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
5090#endif
5091#ifdef TARGET_SPARC64

--- 172 unchanged lines hidden (view full) ---

5264 };
5265 static const char fregnames[32][4] = {
5266 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5267 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5268 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5269 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5270 };
5271
5030 dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
5031 dc->def = &env->def;
5032 dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
5033 dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
5034#ifndef CONFIG_USER_ONLY
5035 dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
5036#endif
5037#ifdef TARGET_SPARC64

--- 172 unchanged lines hidden (view full) ---

5210 };
5211 static const char fregnames[32][4] = {
5212 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5213 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5214 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5215 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5216 };
5217
5272 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
5273#ifdef TARGET_SPARC64
5274 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
5275#endif
5276 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5277 };
5278
5279 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5280#ifdef TARGET_SPARC64
5281 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5282 { &cpu_xcc_Z, offsetof(CPUSPARCState, xcc_Z), "xcc_Z" },
5283 { &cpu_xcc_C, offsetof(CPUSPARCState, xcc_C), "xcc_C" },
5284#endif
5285 { &cpu_cc_N, offsetof(CPUSPARCState, cc_N), "cc_N" },
5286 { &cpu_cc_V, offsetof(CPUSPARCState, cc_V), "cc_V" },
5287 { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" },
5288 { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" },
5289 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5218 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5219#ifdef TARGET_SPARC64
5220 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5221 { &cpu_xcc_Z, offsetof(CPUSPARCState, xcc_Z), "xcc_Z" },
5222 { &cpu_xcc_C, offsetof(CPUSPARCState, xcc_C), "xcc_C" },
5223#endif
5224 { &cpu_cc_N, offsetof(CPUSPARCState, cc_N), "cc_N" },
5225 { &cpu_cc_V, offsetof(CPUSPARCState, cc_V), "cc_V" },
5226 { &cpu_icc_Z, offsetof(CPUSPARCState, icc_Z), "icc_Z" },
5227 { &cpu_icc_C, offsetof(CPUSPARCState, icc_C), "icc_C" },
5228 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5290 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5291 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5292 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5293 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5294 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5295 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5296 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
5297 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
5298 };
5299
5300 unsigned int i;
5301
5302 cpu_regwptr = tcg_global_mem_new_ptr(tcg_env,
5303 offsetof(CPUSPARCState, regwptr),
5304 "regwptr");
5305
5229 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5230 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5231 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5232 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
5233 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
5234 };
5235
5236 unsigned int i;
5237
5238 cpu_regwptr = tcg_global_mem_new_ptr(tcg_env,
5239 offsetof(CPUSPARCState, regwptr),
5240 "regwptr");
5241
5306 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5307 *r32[i].ptr = tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i].name);
5308 }
5309
5310 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5311 *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name);
5312 }
5313
5314 cpu_regs[0] = NULL;
5315 for (i = 1; i < 8; ++i) {
5316 cpu_regs[i] = tcg_global_mem_new(tcg_env,
5317 offsetof(CPUSPARCState, gregs[i]),

--- 6 unchanged lines hidden (view full) ---

5324 gregnames[i]);
5325 }
5326
5327 for (i = 0; i < TARGET_DPREGS; i++) {
5328 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
5329 offsetof(CPUSPARCState, fpr[i]),
5330 fregnames[i]);
5331 }
5242 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5243 *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name);
5244 }
5245
5246 cpu_regs[0] = NULL;
5247 for (i = 1; i < 8; ++i) {
5248 cpu_regs[i] = tcg_global_mem_new(tcg_env,
5249 offsetof(CPUSPARCState, gregs[i]),

--- 6 unchanged lines hidden (view full) ---

5256 gregnames[i]);
5257 }
5258
5259 for (i = 0; i < TARGET_DPREGS; i++) {
5260 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
5261 offsetof(CPUSPARCState, fpr[i]),
5262 fregnames[i]);
5263 }
5264
5265#ifdef TARGET_SPARC64
5266 cpu_fprs = tcg_global_mem_new_i32(tcg_env,
5267 offsetof(CPUSPARCState, fprs), "fprs");
5268#endif
5332}
5333
5334void sparc_restore_state_to_opc(CPUState *cs,
5335 const TranslationBlock *tb,
5336 const uint64_t *data)
5337{
5338 SPARCCPU *cpu = SPARC_CPU(cs);
5339 CPUSPARCState *env = &cpu->env;

--- 17 unchanged lines hidden --- 		5269}
5270
5271void sparc_restore_state_to_opc(CPUState *cs,
5272 const TranslationBlock *tb,
5273 const uint64_t *data)
5274{
5275 SPARCCPU *cpu = SPARC_CPU(cs);
5276 CPUSPARCState *env = &cpu->env;

--- 17 unchanged lines hidden ---