translate.c (52123f14e14233a353f81f87506b3b8c7b38898c) translate.c (36ab4623a894de80c413fa958a5fdb79dc50b1c2)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

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79 bool supervisor;
80#ifdef TARGET_SPARC64
81 bool hypervisor;
82#endif
83#endif
84
85 uint32_t cc_op; /* current CC operation */
86 sparc_def_t *def;
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 70 unchanged lines hidden (view full) ---

79 bool supervisor;
80#ifdef TARGET_SPARC64
81 bool hypervisor;
82#endif
83#endif
84
85 uint32_t cc_op; /* current CC operation */
86 sparc_def_t *def;
87 TCGv_i32 t32[3];
88 int n_t32;
89#ifdef TARGET_SPARC64
90 int fprs_dirty;
91 int asi;
92#endif
93} DisasContext;
94
95typedef struct {
96 TCGCond cond;

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124static int sign_extend(int x, int len)
125{
126 len = 32 - len;
127 return (x << len) >> len;
128}
129
130#define IS_IMM (insn & (1<<13))
131
87#ifdef TARGET_SPARC64
88 int fprs_dirty;
89 int asi;
90#endif
91} DisasContext;
92
93typedef struct {
94 TCGCond cond;

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122static int sign_extend(int x, int len)
123{
124 len = 32 - len;
125 return (x << len) >> len;
126}
127
128#define IS_IMM (insn & (1<<13))
129
132static inline TCGv_i32 get_temp_i32(DisasContext *dc)
133{
134 TCGv_i32 t;
135 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
136 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
137 return t;
138}
139
140static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
141{
142#if defined(TARGET_SPARC64)
143 int bit = (rd < 32) ? 1 : 2;
144 /* If we know we've already set this bit within the TB,
145 we can avoid setting it again. */
146 if (!(dc->fprs_dirty & bit)) {
147 dc->fprs_dirty |= bit;
148 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
149 }
150#endif
151}
152
153/* floating point registers moves */
154static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
155{
130static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
131{
132#if defined(TARGET_SPARC64)
133 int bit = (rd < 32) ? 1 : 2;
134 /* If we know we've already set this bit within the TB,
135 we can avoid setting it again. */
136 if (!(dc->fprs_dirty & bit)) {
137 dc->fprs_dirty |= bit;
138 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
139 }
140#endif
141}
142
143/* floating point registers moves */
144static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
145{
156 TCGv_i32 ret = get_temp_i32(dc);
146 TCGv_i32 ret = tcg_temp_new_i32();
157 if (src & 1) {
158 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
159 } else {
160 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
161 }
162 return ret;
163}
164

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170 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
171 (dst & 1 ? 0 : 32), 32);
172 tcg_temp_free_i64(t);
173 gen_update_fprs_dirty(dc, dst);
174}
175
176static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
177{
147 if (src & 1) {
148 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
149 } else {
150 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
151 }
152 return ret;
153}
154

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160 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
161 (dst & 1 ? 0 : 32), 32);
162 tcg_temp_free_i64(t);
163 gen_update_fprs_dirty(dc, dst);
164}
165
166static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
167{
178 return get_temp_i32(dc);
168 return tcg_temp_new_i32();
179}
180
181static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
182{
183 src = DFPREG(src);
184 return cpu_fpr[src / 2];
185}
186

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5511 TCGv_i64 t64 = tcg_temp_new_i64();
5512 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5513 dc->mem_idx, MO_TEUQ);
5514 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
5515 tcg_temp_free_i64(t64);
5516 break;
5517 }
5518#endif
169}
170
171static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
172{
173 src = DFPREG(src);
174 return cpu_fpr[src / 2];
175}
176

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5501 TCGv_i64 t64 = tcg_temp_new_i64();
5502 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5503 dc->mem_idx, MO_TEUQ);
5504 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
5505 tcg_temp_free_i64(t64);
5506 break;
5507 }
5508#endif
5519 cpu_dst_32 = get_temp_i32(dc);
5509 cpu_dst_32 = tcg_temp_new_i32();
5520 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5521 dc->mem_idx, MO_TEUL);
5522 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
5523 break;
5524 case 0x22: /* ldqf, load quad fpreg */
5525 CHECK_FPU_FEATURE(dc, FLOAT128);
5526 gen_address_mask(dc, cpu_addr);
5527 cpu_src1_64 = tcg_temp_new_i64();

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5758 goto egress;
5759#endif
5760#ifndef TARGET_SPARC64
5761 ncp_insn:
5762 gen_exception(dc, TT_NCP_INSN);
5763 goto egress;
5764#endif
5765 egress:
5510 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5511 dc->mem_idx, MO_TEUL);
5512 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
5513 break;
5514 case 0x22: /* ldqf, load quad fpreg */
5515 CHECK_FPU_FEATURE(dc, FLOAT128);
5516 gen_address_mask(dc, cpu_addr);
5517 cpu_src1_64 = tcg_temp_new_i64();

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5748 goto egress;
5749#endif
5750#ifndef TARGET_SPARC64
5751 ncp_insn:
5752 gen_exception(dc, TT_NCP_INSN);
5753 goto egress;
5754#endif
5755 egress:
5766 if (dc->n_t32 != 0) {
5767 int i;
5768 for (i = dc->n_t32 - 1; i >= 0; --i) {
5769 tcg_temp_free_i32(dc->t32[i]);
5770 }
5771 dc->n_t32 = 0;
5772 }
5773}
5774
5775static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5776{
5777 DisasContext *dc = container_of(dcbase, DisasContext, base);
5778 CPUSPARCState *env = cs->env_ptr;
5779 int bound;
5780

--- 226 unchanged lines hidden --- 		5756}
5757
5758static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
5759{
5760 DisasContext *dc = container_of(dcbase, DisasContext, base);
5761 CPUSPARCState *env = cs->env_ptr;
5762 int bound;
5763

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