translate.c (06c060d9e5bad5c5317cb158fcce2e2ae3f942a8) translate.c (287b11520bd4dafd58e42ccff7010f8c4bbafcf9)
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 2092 unchanged lines hidden (view full) ---

2101 }
2102 }
2103#endif
2104
2105 done:
2106 return (DisasASI){ type, asi, mem_idx, memop };
2107}
2108
1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public

--- 2092 unchanged lines hidden (view full) ---

2101 }
2102 }
2103#endif
2104
2105 done:
2106 return (DisasASI){ type, asi, mem_idx, memop };
2107}
2108
2109static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
2110{
2111 int asi = IS_IMM ? -2 : GET_FIELD(insn, 19, 26);
2112 return resolve_asi(dc, asi, memop);
2113}
2114
2115#if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2116static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
2117 TCGv_i32 asi, TCGv_i32 mop)
2118{
2119 g_assert_not_reached();
2120}
2121
2122static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,

--- 170 unchanged lines hidden (view full) ---

2293
2294 /* End the TB. */
2295 dc->npc = DYNAMIC_PC;
2296 }
2297 break;
2298 }
2299}
2300
2109#if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2110static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a,
2111 TCGv_i32 asi, TCGv_i32 mop)
2112{
2113 g_assert_not_reached();
2114}
2115
2116static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r,

--- 170 unchanged lines hidden (view full) ---

2287
2288 /* End the TB. */
2289 dc->npc = DYNAMIC_PC;
2290 }
2291 break;
2292 }
2293}
2294
2301static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
2302 TCGv addr, int rd)
2295static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
2296 TCGv addr, int rd)
2303{
2304 MemOp memop = da->memop;
2305 MemOp size = memop & MO_SIZE;
2306 TCGv_i32 d32;
2307 TCGv_i64 d64;
2297{
2298 MemOp memop = da->memop;
2299 MemOp size = memop & MO_SIZE;
2300 TCGv_i32 d32;
2301 TCGv_i64 d64;
2302 TCGv addr_tmp;
2308
2309 /* TODO: Use 128-bit load/store below. */
2310 if (size == MO_128) {
2311 memop = (memop & ~MO_SIZE) | MO_64;
2312 }
2313
2314 switch (da->type) {
2315 case GET_ASI_EXCP:

--- 10 unchanged lines hidden (view full) ---

2326
2327 case MO_64:
2328 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop);
2329 break;
2330
2331 case MO_128:
2332 d64 = tcg_temp_new_i64();
2333 tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
2303
2304 /* TODO: Use 128-bit load/store below. */
2305 if (size == MO_128) {
2306 memop = (memop & ~MO_SIZE) | MO_64;
2307 }
2308
2309 switch (da->type) {
2310 case GET_ASI_EXCP:

--- 10 unchanged lines hidden (view full) ---

2321
2322 case MO_64:
2323 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop);
2324 break;
2325
2326 case MO_128:
2327 d64 = tcg_temp_new_i64();
2328 tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
2334 tcg_gen_addi_tl(addr, addr, 8);
2335 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop);
2329 addr_tmp = tcg_temp_new();
2330 tcg_gen_addi_tl(addr_tmp, addr, 8);
2331 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
2336 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2337 break;
2338 default:
2339 g_assert_not_reached();
2340 }
2341 break;
2342
2343 case GET_ASI_BLOCK:
2344 /* Valid for lddfa on aligned registers only. */
2345 if (orig_size == MO_64 && (rd & 7) == 0) {
2332 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2333 break;
2334 default:
2335 g_assert_not_reached();
2336 }
2337 break;
2338
2339 case GET_ASI_BLOCK:
2340 /* Valid for lddfa on aligned registers only. */
2341 if (orig_size == MO_64 && (rd & 7) == 0) {
2346 TCGv eight;
2347 int i;
2348
2349 /* The first operation checks required alignment. */
2342 /* The first operation checks required alignment. */
2350 eight = tcg_constant_tl(8);
2351 for (i = 0; ; ++i) {
2343 addr_tmp = tcg_temp_new();
2344 for (int i = 0; ; ++i) {
2352 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
2353 memop | (i == 0 ? MO_ALIGN_64 : 0));
2354 if (i == 7) {
2355 break;
2356 }
2345 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
2346 memop | (i == 0 ? MO_ALIGN_64 : 0));
2347 if (i == 7) {
2348 break;
2349 }
2357 tcg_gen_add_tl(addr, addr, eight);
2350 tcg_gen_addi_tl(addr_tmp, addr, 8);
2351 addr = addr_tmp;
2358 }
2359 } else {
2360 gen_exception(dc, TT_ILL_INSN);
2361 }
2362 break;
2363
2364 case GET_ASI_SHORT:
2365 /* Valid for lddfa only. */

--- 25 unchanged lines hidden (view full) ---

2391 break;
2392 case MO_64:
2393 gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr,
2394 r_asi, r_mop);
2395 break;
2396 case MO_128:
2397 d64 = tcg_temp_new_i64();
2398 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
2352 }
2353 } else {
2354 gen_exception(dc, TT_ILL_INSN);
2355 }
2356 break;
2357
2358 case GET_ASI_SHORT:
2359 /* Valid for lddfa only. */

--- 25 unchanged lines hidden (view full) ---

2385 break;
2386 case MO_64:
2387 gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr,
2388 r_asi, r_mop);
2389 break;
2390 case MO_128:
2391 d64 = tcg_temp_new_i64();
2392 gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
2399 tcg_gen_addi_tl(addr, addr, 8);
2400 gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr,
2393 addr_tmp = tcg_temp_new();
2394 tcg_gen_addi_tl(addr_tmp, addr, 8);
2395 gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp,
2401 r_asi, r_mop);
2402 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2403 break;
2404 default:
2405 g_assert_not_reached();
2406 }
2407 }
2408 break;
2409 }
2410}
2411
2396 r_asi, r_mop);
2397 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2398 break;
2399 default:
2400 g_assert_not_reached();
2401 }
2402 }
2403 break;
2404 }
2405}
2406
2412static void __attribute__((unused))
2413gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
2407static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
2408 TCGv addr, int rd)
2414{
2409{
2415 MemOp sz = ctz32(size);
2416 DisasASI da = get_asi(dc, insn, MO_TE | sz);
2417
2418 gen_address_mask(dc, addr);
2419 gen_ldf_asi0(dc, &da, sz, addr, rd);
2420}
2421
2422static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
2423 TCGv addr, int rd)
2424{
2425 MemOp memop = da->memop;
2426 MemOp size = memop & MO_SIZE;
2427 TCGv_i32 d32;
2410 MemOp memop = da->memop;
2411 MemOp size = memop & MO_SIZE;
2412 TCGv_i32 d32;
2413 TCGv addr_tmp;
2428
2429 /* TODO: Use 128-bit load/store below. */
2430 if (size == MO_128) {
2431 memop = (memop & ~MO_SIZE) | MO_64;
2432 }
2433
2434 switch (da->type) {
2435 case GET_ASI_EXCP:

--- 13 unchanged lines hidden (view full) ---

2449 case MO_128:
2450 /* Only 4-byte alignment required. However, it is legal for the
2451 cpu to signal the alignment fault, and the OS trap handler is
2452 required to fix it up. Requiring 16-byte alignment here avoids
2453 having to probe the second page before performing the first
2454 write. */
2455 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
2456 memop | MO_ALIGN_16);
2414
2415 /* TODO: Use 128-bit load/store below. */
2416 if (size == MO_128) {
2417 memop = (memop & ~MO_SIZE) | MO_64;
2418 }
2419
2420 switch (da->type) {
2421 case GET_ASI_EXCP:

--- 13 unchanged lines hidden (view full) ---

2435 case MO_128:
2436 /* Only 4-byte alignment required. However, it is legal for the
2437 cpu to signal the alignment fault, and the OS trap handler is
2438 required to fix it up. Requiring 16-byte alignment here avoids
2439 having to probe the second page before performing the first
2440 write. */
2441 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
2442 memop | MO_ALIGN_16);
2457 tcg_gen_addi_tl(addr, addr, 8);
2458 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop);
2443 addr_tmp = tcg_temp_new();
2444 tcg_gen_addi_tl(addr_tmp, addr, 8);
2445 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
2459 break;
2460 default:
2461 g_assert_not_reached();
2462 }
2463 break;
2464
2465 case GET_ASI_BLOCK:
2466 /* Valid for stdfa on aligned registers only. */
2467 if (orig_size == MO_64 && (rd & 7) == 0) {
2446 break;
2447 default:
2448 g_assert_not_reached();
2449 }
2450 break;
2451
2452 case GET_ASI_BLOCK:
2453 /* Valid for stdfa on aligned registers only. */
2454 if (orig_size == MO_64 && (rd & 7) == 0) {
2468 TCGv eight;
2469 int i;
2470
2471 /* The first operation checks required alignment. */
2455 /* The first operation checks required alignment. */
2472 eight = tcg_constant_tl(8);
2473 for (i = 0; ; ++i) {
2456 addr_tmp = tcg_temp_new();
2457 for (int i = 0; ; ++i) {
2474 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
2475 memop | (i == 0 ? MO_ALIGN_64 : 0));
2476 if (i == 7) {
2477 break;
2478 }
2458 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
2459 memop | (i == 0 ? MO_ALIGN_64 : 0));
2460 if (i == 7) {
2461 break;
2462 }
2479 tcg_gen_add_tl(addr, addr, eight);
2463 tcg_gen_addi_tl(addr_tmp, addr, 8);
2464 addr = addr_tmp;
2480 }
2481 } else {
2482 gen_exception(dc, TT_ILL_INSN);
2483 }
2484 break;
2485
2486 case GET_ASI_SHORT:
2487 /* Valid for stdfa only. */

--- 9 unchanged lines hidden (view full) ---

2497 /* According to the table in the UA2011 manual, the only
2498 other asis that are valid for ldfa/lddfa/ldqfa are
2499 the PST* asis, which aren't currently handled. */
2500 gen_exception(dc, TT_ILL_INSN);
2501 break;
2502 }
2503}
2504
2465 }
2466 } else {
2467 gen_exception(dc, TT_ILL_INSN);
2468 }
2469 break;
2470
2471 case GET_ASI_SHORT:
2472 /* Valid for stdfa only. */

--- 9 unchanged lines hidden (view full) ---

2482 /* According to the table in the UA2011 manual, the only
2483 other asis that are valid for ldfa/lddfa/ldqfa are
2484 the PST* asis, which aren't currently handled. */
2485 gen_exception(dc, TT_ILL_INSN);
2486 break;
2487 }
2488}
2489
2505static void __attribute__((unused))
2506gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
2507{
2508 MemOp sz = ctz32(size);
2509 DisasASI da = get_asi(dc, insn, MO_TE | sz);
2510
2511 gen_address_mask(dc, addr);
2512 gen_stf_asi0(dc, &da, sz, addr, rd);
2513}
2514
2515static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
2516{
2517 TCGv hi = gen_dest_gpr(dc, rd);
2518 TCGv lo = gen_dest_gpr(dc, rd + 1);
2519
2520 switch (da->type) {
2521 case GET_ASI_EXCP:
2522 return;

--- 2122 unchanged lines hidden (view full) ---

4645 }
4646 if (gen_trap_ifnofpu(dc)) {
4647 return true;
4648 }
4649 if (sz == MO_128 && gen_trap_float128(dc)) {
4650 return true;
4651 }
4652 da = resolve_asi(dc, a->asi, MO_TE | sz);
2490static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
2491{
2492 TCGv hi = gen_dest_gpr(dc, rd);
2493 TCGv lo = gen_dest_gpr(dc, rd + 1);
2494
2495 switch (da->type) {
2496 case GET_ASI_EXCP:
2497 return;

--- 2122 unchanged lines hidden (view full) ---

4620 }
4621 if (gen_trap_ifnofpu(dc)) {
4622 return true;
4623 }
4624 if (sz == MO_128 && gen_trap_float128(dc)) {
4625 return true;
4626 }
4627 da = resolve_asi(dc, a->asi, MO_TE | sz);
4653 gen_ldf_asi0(dc, &da, sz, addr, a->rd);
4628 gen_ldf_asi(dc, &da, sz, addr, a->rd);
4654 gen_update_fprs_dirty(dc, a->rd);
4655 return advance_pc(dc);
4656}
4657
4658TRANS(LDF, ALL, do_ld_fpr, a, MO_32)
4659TRANS(LDDF, ALL, do_ld_fpr, a, MO_64)
4660TRANS(LDQF, ALL, do_ld_fpr, a, MO_128)
4661
4629 gen_update_fprs_dirty(dc, a->rd);
4630 return advance_pc(dc);
4631}
4632
4633TRANS(LDF, ALL, do_ld_fpr, a, MO_32)
4634TRANS(LDDF, ALL, do_ld_fpr, a, MO_64)
4635TRANS(LDQF, ALL, do_ld_fpr, a, MO_128)
4636
4637TRANS(LDFA, 64, do_ld_fpr, a, MO_32)
4638TRANS(LDDFA, 64, do_ld_fpr, a, MO_64)
4639TRANS(LDQFA, 64, do_ld_fpr, a, MO_128)
4640
4662static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
4663{
4664 TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
4665 DisasASI da;
4666
4667 if (addr == NULL) {
4668 return false;
4669 }
4670 if (gen_trap_ifnofpu(dc)) {
4671 return true;
4672 }
4673 if (sz == MO_128 && gen_trap_float128(dc)) {
4674 return true;
4675 }
4676 da = resolve_asi(dc, a->asi, MO_TE | sz);
4641static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
4642{
4643 TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
4644 DisasASI da;
4645
4646 if (addr == NULL) {
4647 return false;
4648 }
4649 if (gen_trap_ifnofpu(dc)) {
4650 return true;
4651 }
4652 if (sz == MO_128 && gen_trap_float128(dc)) {
4653 return true;
4654 }
4655 da = resolve_asi(dc, a->asi, MO_TE | sz);
4677 gen_stf_asi0(dc, &da, sz, addr, a->rd);
4656 gen_stf_asi(dc, &da, sz, addr, a->rd);
4678 return advance_pc(dc);
4679}
4680
4681TRANS(STF, ALL, do_st_fpr, a, MO_32)
4682TRANS(STDF, ALL, do_st_fpr, a, MO_64)
4683TRANS(STQF, ALL, do_st_fpr, a, MO_128)
4684
4657 return advance_pc(dc);
4658}
4659
4660TRANS(STF, ALL, do_st_fpr, a, MO_32)
4661TRANS(STDF, ALL, do_st_fpr, a, MO_64)
4662TRANS(STQF, ALL, do_st_fpr, a, MO_128)
4663
4664TRANS(STFA, 64, do_st_fpr, a, MO_32)
4665TRANS(STDFA, 64, do_st_fpr, a, MO_64)
4666TRANS(STQFA, 64, do_st_fpr, a, MO_128)
4667
4685static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
4686{
4687 if (!avail_32(dc)) {
4688 return false;
4689 }
4690 if (!supervisor(dc)) {
4691 return raise_priv(dc);
4692 }

--- 817 unchanged lines hidden (view full) ---

5510 rs2 = GET_FIELD(insn, 27, 31);
5511 if (rs2 != 0) {
5512 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
5513 }
5514 }
5515 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5516 (xop > 0x17 && xop <= 0x1d ) ||
5517 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4668static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
4669{
4670 if (!avail_32(dc)) {
4671 return false;
4672 }
4673 if (!supervisor(dc)) {
4674 return raise_priv(dc);
4675 }

--- 817 unchanged lines hidden (view full) ---

5493 rs2 = GET_FIELD(insn, 27, 31);
5494 if (rs2 != 0) {
5495 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
5496 }
5497 }
5498 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5499 (xop > 0x17 && xop <= 0x1d ) ||
5500 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
5518 TCGv cpu_val = gen_dest_gpr(dc, rd);
5519
5520 switch (xop) {
5521 case 0x0: /* ld, V9 lduw, load unsigned word */
5522 case 0x1: /* ldub, load unsigned byte */
5523 case 0x2: /* lduh, load unsigned halfword */
5524 case 0x3: /* ldd, load double word */
5525 case 0x9: /* ldsb, load signed byte */
5526 case 0xa: /* ldsh, load signed halfword */
5527 case 0xd: /* ldstub */
5528 case 0x0f: /* swap */
5529 case 0x10: /* lda, V9 lduwa, load word alternate */
5530 case 0x11: /* lduba, load unsigned byte alternate */
5531 case 0x12: /* lduha, load unsigned halfword alternate */
5532 case 0x13: /* ldda, load double word alternate */
5533 case 0x19: /* ldsba, load signed byte alternate */
5534 case 0x1a: /* ldsha, load signed halfword alternate */
5535 case 0x1d: /* ldstuba */
5536 case 0x1f: /* swapa */
5537 g_assert_not_reached(); /* in decodetree */
5538 case 0x08: /* V9 ldsw */
5539 case 0x0b: /* V9 ldx */
5540 case 0x18: /* V9 ldswa */
5541 case 0x1b: /* V9 ldxa */
5542 case 0x2d: /* V9 prefetch */
5543 case 0x3d: /* V9 prefetcha */
5544 goto illegal_insn; /* in decodetree */
5545#ifdef TARGET_SPARC64
5546 case 0x30: /* V9 ldfa */
5547 if (gen_trap_ifnofpu(dc)) {
5548 goto jmp_insn;
5549 }
5550 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
5551 gen_update_fprs_dirty(dc, rd);
5552 goto skip_move;
5553 case 0x33: /* V9 lddfa */
5554 if (gen_trap_ifnofpu(dc)) {
5555 goto jmp_insn;
5556 }
5557 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
5558 gen_update_fprs_dirty(dc, DFPREG(rd));
5559 goto skip_move;
5560 case 0x32: /* V9 ldqfa */
5561 CHECK_FPU_FEATURE(dc, FLOAT128);
5562 if (gen_trap_ifnofpu(dc)) {
5563 goto jmp_insn;
5564 }
5565 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
5566 gen_update_fprs_dirty(dc, QFPREG(rd));
5567 goto skip_move;
5568#endif
5569 default:
5570 goto illegal_insn;
5571 }
5572 gen_store_gpr(dc, rd, cpu_val);
5573#if defined(TARGET_SPARC64)
5574 skip_move: ;
5575#endif
5501 goto illegal_insn; /* in decodetree */
5576 } else if (xop >= 0x20 && xop < 0x24) {
5577 if (gen_trap_ifnofpu(dc)) {
5578 goto jmp_insn;
5579 }
5580 switch (xop) {
5581 case 0x20: /* ldf, load fpreg */
5582 case 0x22: /* ldqf, load quad fpreg */
5583 case 0x23: /* lddf, load double fpreg */

--- 39 unchanged lines hidden (view full) ---

5623 tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
5624 dc->mem_idx, MO_TEUL | MO_ALIGN);
5625 }
5626 break;
5627 default:
5628 goto illegal_insn;
5629 }
5630 } else if (xop > 0x33 && xop < 0x3f) {
5502 } else if (xop >= 0x20 && xop < 0x24) {
5503 if (gen_trap_ifnofpu(dc)) {
5504 goto jmp_insn;
5505 }
5506 switch (xop) {
5507 case 0x20: /* ldf, load fpreg */
5508 case 0x22: /* ldqf, load quad fpreg */
5509 case 0x23: /* lddf, load double fpreg */

--- 39 unchanged lines hidden (view full) ---

5549 tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
5550 dc->mem_idx, MO_TEUL | MO_ALIGN);
5551 }
5552 break;
5553 default:
5554 goto illegal_insn;
5555 }
5556 } else if (xop > 0x33 && xop < 0x3f) {
5631 switch (xop) {
5632#ifdef TARGET_SPARC64
5633 case 0x34: /* V9 stfa */
5634 if (gen_trap_ifnofpu(dc)) {
5635 goto jmp_insn;
5636 }
5637 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
5638 break;
5639 case 0x36: /* V9 stqfa */
5640 {
5641 CHECK_FPU_FEATURE(dc, FLOAT128);
5642 if (gen_trap_ifnofpu(dc)) {
5643 goto jmp_insn;
5644 }
5645 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
5646 }
5647 break;
5648 case 0x37: /* V9 stdfa */
5649 if (gen_trap_ifnofpu(dc)) {
5650 goto jmp_insn;
5651 }
5652 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
5653 break;
5654#endif
5655 case 0x3e: /* V9 casxa */
5656 case 0x3c: /* V9 or LEON3 casa */
5657 goto illegal_insn; /* in decodetree */
5658 default:
5659 goto illegal_insn;
5660 }
5557 goto illegal_insn; /* in decodetree */
5661 } else {
5662 goto illegal_insn;
5663 }
5664 }
5665 break;
5666 }
5667 advance_pc(dc);
5668 jmp_insn:

--- 287 unchanged lines hidden --- 		5558 } else {
5559 goto illegal_insn;
5560 }
5561 }
5562 break;
5563 }
5564 advance_pc(dc);
5565 jmp_insn:

--- 287 unchanged lines hidden ---