int32_helper.c (e692f9c6a681de1372a41999b14a947a553b6a1a) int32_helper.c (c35c8d4d1a1e7b556158b23fb90719f44ac98966)
1/*
2 * Sparc32 interrupt helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu/main-loop.h"
22#include "cpu.h"
23#include "trace.h"
1/*
2 * Sparc32 interrupt helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu/main-loop.h"
22#include "cpu.h"
23#include "trace.h"
24#include "exec/cpu_ldst.h"
24#include "exec/log.h"
25#include "sysemu/runstate.h"
26
25#include "exec/log.h"
26#include "sysemu/runstate.h"
27
27
28static const char * const excp_names[0x80] = {
29 [TT_TFAULT] = "Instruction Access Fault",
30 [TT_ILL_INSN] = "Illegal Instruction",
31 [TT_PRIV_INSN] = "Privileged Instruction",
32 [TT_NFPU_INSN] = "FPU Disabled",
33 [TT_WIN_OVF] = "Window Overflow",
34 [TT_WIN_UNF] = "Window Underflow",
35 [TT_UNALIGNED] = "Unaligned Memory Access",

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111 } else if (intno >= 0x80) {
112 name = "Trap Instruction";
113 } else {
114 name = excp_name_str(intno);
115 }
116
117 qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
118 log_cpu_state(cs, 0);
28static const char * const excp_names[0x80] = {
29 [TT_TFAULT] = "Instruction Access Fault",
30 [TT_ILL_INSN] = "Illegal Instruction",
31 [TT_PRIV_INSN] = "Privileged Instruction",
32 [TT_NFPU_INSN] = "FPU Disabled",
33 [TT_WIN_OVF] = "Window Overflow",
34 [TT_WIN_UNF] = "Window Underflow",
35 [TT_UNALIGNED] = "Unaligned Memory Access",

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111 } else if (intno >= 0x80) {
112 name = "Trap Instruction";
113 } else {
114 name = excp_name_str(intno);
115 }
116
117 qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
118 log_cpu_state(cs, 0);
119#if 0
120 {
121 int i;
122 uint8_t *ptr;
123
124 qemu_log(" code=");
125 ptr = (uint8_t *)env->pc;
126 for (i = 0; i < 16; i++) {
127 qemu_log(" %02x", ldub(ptr + i));
128 }
129 qemu_log("\n");
130 }
131#endif
132 count++;
133 }
119 count++;
120 }
134#if !defined(CONFIG_USER_ONLY)
121#ifndef CONFIG_USER_ONLY
135 if (env->psret == 0) {
136 if (cs->exception_index == 0x80 &&
137 env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
138 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
139 } else {
140 cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
141 "Error state",
142 cs->exception_index, excp_name_str(cs->exception_index));
143 }
144 return;
145 }
122 if (env->psret == 0) {
123 if (cs->exception_index == 0x80 &&
124 env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
125 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
126 } else {
127 cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
128 "Error state",
129 cs->exception_index, excp_name_str(cs->exception_index));
130 }
131 return;
132 }
133 if (intno == TT_FP_EXCP) {
134 /*
135 * The sparc32 fpu has three states related to exception handling.
136 * The FPop that signals an exception transitions from fp_execute
137 * to fp_exception_pending. A subsequent FPop transitions from
138 * fp_exception_pending to fp_exception, which forces the trap.
139 *
140 * If the queue is not empty, this trap is due to execution of an
141 * illegal FPop while in fp_exception state. Here we are to
142 * re-enter fp_exception_pending state without queuing the insn.
143 *
144 * We do not model the fp_exception_pending state, but instead
145 * skip directly to fp_exception state. We advance pc/npc to
146 * mimic delayed trap delivery as if by the subsequent insn.
147 */
148 if (!env->fsr_qne) {
149 env->fsr_qne = FSR_QNE;
150 env->fq.s.addr = env->pc;
151 env->fq.s.insn = cpu_ldl_code(env, env->pc);
152 }
153 env->pc = env->npc;
154 env->npc = env->npc + 4;
155 }
146#endif
147 env->psret = 0;
148 cwp = cpu_cwp_dec(env, env->cwp - 1);
149 cpu_set_cwp(env, cwp);
150 env->regwptr[9] = env->pc;
151 env->regwptr[10] = env->npc;
152 env->psrps = env->psrs;
153 env->psrs = 1;

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157 env->psret = 0;
158 cwp = cpu_cwp_dec(env, env->cwp - 1);
159 cpu_set_cwp(env, cwp);
160 env->regwptr[9] = env->pc;
161 env->regwptr[10] = env->npc;
162 env->psrps = env->psrs;
163 env->psrs = 1;

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