| insns.decode (e8325dc02d059685331d8607d5e620328bac594e) | insns.decode (0faef01b3989bb1fb6e0ed73ffa909e77b79f780) |
|---|---|
| 1# SPDX-License-Identifier: LGPL-2.0+ 2# 3# Sparc instruction decode definitions. 4# Copyright (c) 2023 Richard Henderson <rth@twiddle.net> 5 6## 7## Major Opcodes 00 and 01 -- branches, call, and sethi. 8## --- 8 unchanged lines hidden (view full) --- 17BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 18 19NCP 00 - ---- 111 ---------------------- # CBcc 20 21SETHI 00 rd:5 100 i:22 22 23CALL 01 i:s30 24 | 1# SPDX-License-Identifier: LGPL-2.0+ 2# 3# Sparc instruction decode definitions. 4# Copyright (c) 2023 Richard Henderson <rth@twiddle.net> 5 6## 7## Major Opcodes 00 and 01 -- branches, call, and sethi. 8## --- 8 unchanged lines hidden (view full) --- 17BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 18 19NCP 00 - ---- 111 ---------------------- # CBcc 20 21SETHI 00 rd:5 100 i:22 22 23CALL 01 i:s30 24 |
| 25## 26## Major Opcode 10 -- integer, floating-point, vis, and system insns. 27## 28 29&r_r_ri rd rs1 rs2_or_imm imm:bool 30@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 31 |
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| 25{ 26 [ 27 STBAR 10 00000 101000 01111 0 0000000000000 28 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 29 30 RDCCR 10 rd:5 101000 00010 0 0000000000000 31 RDASI 10 rd:5 101000 00011 0 0000000000000 32 RDTICK 10 rd:5 101000 00100 0 0000000000000 --- 7 unchanged lines hidden (view full) --- 40 RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 41 RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 42 ] 43 # Before v8, all rs1 accepted; otherwise rs1==0. 44 RDY 10 rd:5 101000 rs1:5 0 0000000000000 45} 46 47{ | 32{ 33 [ 34 STBAR 10 00000 101000 01111 0 0000000000000 35 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 36 37 RDCCR 10 rd:5 101000 00010 0 0000000000000 38 RDASI 10 rd:5 101000 00011 0 0000000000000 39 RDTICK 10 rd:5 101000 00100 0 0000000000000 --- 7 unchanged lines hidden (view full) --- 47 RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 48 RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 49 ] 50 # Before v8, all rs1 accepted; otherwise rs1==0. 51 RDY 10 rd:5 101000 rs1:5 0 0000000000000 52} 53 54{ |
| 55 [ 56 WRY 10 00000 110000 ..... . ............. @n_r_ri 57 WRCCR 10 00010 110000 ..... . ............. @n_r_ri 58 WRASI 10 00011 110000 ..... . ............. @n_r_ri 59 WRFPRS 10 00110 110000 ..... . ............. @n_r_ri 60 { 61 WRGSR 10 10011 110000 ..... . ............. @n_r_ri 62 WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri 63 } 64 WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri 65 WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri 66 WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri 67 WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri 68 WRSTICK 10 11000 110000 ..... . ............. @n_r_ri 69 WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri 70 ] 71 # Before v8, rs1==0 was WRY, and the rest executed as nop. 72 [ 73 NOP_v7 10 ----- 110000 ----- 0 00000000 ----- 74 NOP_v7 10 ----- 110000 ----- 1 -------- ----- 75 ] 76} 77 78{ |
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| 48 RDPSR 10 rd:5 101001 00000 0 0000000000000 49 RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 50} 51RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 52RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 53RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 54RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 55RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 --- 40 unchanged lines hidden --- | 79 RDPSR 10 rd:5 101001 00000 0 0000000000000 80 RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 81} 82RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 83RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 84RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 85RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 86RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 --- 40 unchanged lines hidden --- |