insns.decode (bb97f2f5d77227cc6b5edeed637218e7dd214816) insns.decode (428881deba62aa8fd5ef9248deba79594f70615a)
1# SPDX-License-Identifier: LGPL-2.0+
2#
3# Sparc instruction decode definitions.
4# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
5
6##
7## Major Opcodes 00 and 01 -- branches, call, and sethi.
8##

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24
25##
26## Major Opcode 10 -- integer, floating-point, vis, and system insns.
27##
28
29&r_r_ri rd rs1 rs2_or_imm imm:bool
30@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
31
1# SPDX-License-Identifier: LGPL-2.0+
2#
3# Sparc instruction decode definitions.
4# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
5
6##
7## Major Opcodes 00 and 01 -- branches, call, and sethi.
8##

--- 15 unchanged lines hidden (view full) ---

24
25##
26## Major Opcode 10 -- integer, floating-point, vis, and system insns.
27##
28
29&r_r_ri rd rs1 rs2_or_imm imm:bool
30@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
31
32&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
33@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
34
32{
33 [
34 STBAR 10 00000 101000 01111 0 0000000000000
35 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
36
37 RDCCR 10 rd:5 101000 00010 0 0000000000000
38 RDASI 10 rd:5 101000 00011 0 0000000000000
39 RDTICK 10 rd:5 101000 00100 0 0000000000000

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147 WRTBR 10 00000 110011 ..... . ............. @n_r_ri
148 WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri
149}
150WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri
151WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
152WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
153WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
154
35{
36 [
37 STBAR 10 00000 101000 01111 0 0000000000000
38 MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
39
40 RDCCR 10 rd:5 101000 00010 0 0000000000000
41 RDASI 10 rd:5 101000 00011 0 0000000000000
42 RDTICK 10 rd:5 101000 00100 0 0000000000000

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150 WRTBR 10 00000 110011 ..... . ............. @n_r_ri
151 WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri
152}
153WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri
154WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
155WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
156WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
157
158ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc
159AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc
160OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc
161XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc
162SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc
163ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc
164ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
165XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
166
155Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
156{
157 # For v7, the entire simm13 field is present, but masked to 7 bits.
158 # For v8, [12:7] are reserved. However, a compatibility note for
159 # the Tcc insn in the v9 manual suggests that the v8 reserved field
160 # was ignored and did not produce traps.
161 Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
162
163 # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
164 # Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
165 Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
166}
167Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
168{
169 # For v7, the entire simm13 field is present, but masked to 7 bits.
170 # For v8, [12:7] are reserved. However, a compatibility note for
171 # the Tcc insn in the v9 manual suggests that the v8 reserved field
172 # was ignored and did not produce traps.
173 Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
174
175 # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
176 # Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
177 Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
178}