cpu.h (cbc3a6a4cc675516328a2b0d3602355d68b6302d) cpu.h (84f8f5876628963e67f66edde8a71208c4274ac8)
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY

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225
226/* 3 <= NWINDOWS <= 32. */
227#define MIN_NWINDOWS 3
228#define MAX_NWINDOWS 32
229
230#if !defined(TARGET_SPARC64)
231#define NB_MMU_MODES 3
232#else
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY

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225
226/* 3 <= NWINDOWS <= 32. */
227#define MIN_NWINDOWS 3
228#define MAX_NWINDOWS 32
229
230#if !defined(TARGET_SPARC64)
231#define NB_MMU_MODES 3
232#else
233#define NB_MMU_MODES 7
233#define NB_MMU_MODES 6
234typedef struct trap_state {
235 uint64_t tpc;
236 uint64_t tnpc;
237 uint64_t tstate;
238 uint32_t tt;
239} trap_state;
240#endif
241#define TARGET_INSN_START_EXTRA_WORDS 1

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671
672/* MMU modes definitions */
673#if defined (TARGET_SPARC64)
674#define MMU_USER_IDX 0
675#define MMU_USER_SECONDARY_IDX 1
676#define MMU_KERNEL_IDX 2
677#define MMU_KERNEL_SECONDARY_IDX 3
678#define MMU_NUCLEUS_IDX 4
234typedef struct trap_state {
235 uint64_t tpc;
236 uint64_t tnpc;
237 uint64_t tstate;
238 uint32_t tt;
239} trap_state;
240#endif
241#define TARGET_INSN_START_EXTRA_WORDS 1

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671
672/* MMU modes definitions */
673#if defined (TARGET_SPARC64)
674#define MMU_USER_IDX 0
675#define MMU_USER_SECONDARY_IDX 1
676#define MMU_KERNEL_IDX 2
677#define MMU_KERNEL_SECONDARY_IDX 3
678#define MMU_NUCLEUS_IDX 4
679#define MMU_HYPV_IDX 5
680#define MMU_PHYS_IDX 6
679#define MMU_PHYS_IDX 5
681#else
682#define MMU_USER_IDX 0
683#define MMU_KERNEL_IDX 1
684#define MMU_PHYS_IDX 2
685#endif
686
687#if defined (TARGET_SPARC64)
688static inline int cpu_has_hypervisor(CPUSPARCState *env1)

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718 }
719#else
720 /* IMMU or DMMU disabled. */
721 if (ifetch
722 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
723 : (env->lsu & DMMU_E) == 0) {
724 return MMU_PHYS_IDX;
725 } else if (cpu_hypervisor_mode(env)) {
680#else
681#define MMU_USER_IDX 0
682#define MMU_KERNEL_IDX 1
683#define MMU_PHYS_IDX 2
684#endif
685
686#if defined (TARGET_SPARC64)
687static inline int cpu_has_hypervisor(CPUSPARCState *env1)

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717 }
718#else
719 /* IMMU or DMMU disabled. */
720 if (ifetch
721 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
722 : (env->lsu & DMMU_E) == 0) {
723 return MMU_PHYS_IDX;
724 } else if (cpu_hypervisor_mode(env)) {
726 return MMU_HYPV_IDX;
725 return MMU_PHYS_IDX;
727 } else if (env->tl > 0) {
728 return MMU_NUCLEUS_IDX;
729 } else if (cpu_supervisor_mode(env)) {
730 return MMU_KERNEL_IDX;
731 } else {
732 return MMU_USER_IDX;
733 }
734#endif

--- 97 unchanged lines hidden --- 		726 } else if (env->tl > 0) {
727 return MMU_NUCLEUS_IDX;
728 } else if (cpu_supervisor_mode(env)) {
729 return MMU_KERNEL_IDX;
730 } else {
731 return MMU_USER_IDX;
732 }
733#endif

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